MC141585 데이터 시트보기 (PDF) - Motorola => Freescale
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MC141585 Datasheet PDF : 27 Pages
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M Pixels
N Horizontal Lines
WINDOW AREA
N Horizontal Lines
NOTE:
M and N are defined in the
frame control registers
located at row 15 column 16
and column 17.
Shadow color is defined by
by registers located at row 16
column 2 and 3.
M Pixels
Window Shadowing
Frame Control Register Row 15 Coln 16
7
65
4
3
2
1
0
ROW 15
COLN 16 WW41 WW40 WW31 WW30 WW21 WW20 WW11 WW10
Bit 7-6 WW41, WW40 - It determines the shadow width
of the window 4 when the window shadowing function is
activated. Please refer to the following table for more
details where M is the actual pixel number of the shadow-
ing.
Table 2. Shadow Width Setting
(WW41, WW40)
Shadow Width M
(unit in Pixel)
(0, 0) (0, 1) (1, 0) (1, 1)
2
4
6
8
Bit 5-4 WW31, WW30 - Similarly as WW41, WW40,
these two bits determine the shadow width of the window 3
when the window shadowing function is activated.
Bit 3-2 WW21, WW20 - Similarly as WW41, WW40,
these two bits determine the shadow width of the window 2
when the window shadowing function is activated.
Bit 1-0 WW11, WW10 - Similarly as WW41, WW40,
these two bits determine the shadow width of the window 1
when the window shadowing function is activated
Frame Control Register Row 15 Coln 17
7
65
4
3
2
1
0
ROW 15
COLN 17 WH41 WH40 WH31 WH30 WH21 WH20 WH11 WH10
Bit 5-4 WH31, WH30 - Similarly as WH41, WH40, these
two bits determine the shadow height of the window 3 when
the window shadowing function is activated.
Bit 3-2 WH21, WH20 - Similarly as WH41, WH40, these
two bits determine the shadow height of the window 2 when
the window shadowing function is activated.
Bit 1-0 WH11, WH10 - Similarly as WH41, WH40, these
two bits determine the shadow height of the window 1 when
the window shadowing function is activated.
Frame Control Register Row 15 Coln 18
7
ROW 15
COLN 18 MSB
6
5
4
RSPACE
3
2
1
0
LSB TRIC HPOL VPOL
Bit 7-3 RSPACE - These 5 bits define the row to row spac-
ing in unit of horizontal scan line. It means extra N lines,
defined by this 5-bit value, will be appended for each display
row. Because of the nonuniform expansion of BRM used by
character height control, this register is usually used to main-
tain the constant OSD menu height for different display
modes instead of adjusting the character height. The default
value of it is 0. It means there is no any extra line inserted
between row and row after power on. It can be used for Por-
trait monitor too when icon design is rotated 90 degree.
Bit 2 TRIC - Tri-state Control. This bit is used to control
the driving state of output pins, R, G, B and FBKG when the
OSD is disabled. After power on, this bit is reset and R, G, B
and FBKG are in high impedance state while OSD being dis-
abled. If it is set by MCU, these four output pins will drive low
while OSD being in disabled state. Basically, the setting is
dependent on the requirement of the external application cir-
cuit.
Bit 1 HPOL - This bit selects the polarity of the incom-
ing horizontal sync signal (HSYNC). If it is negative polarity,
clear this bit. Otherwise, set this bit to 1 to represent the pos-
itive H sync signal. After power on, this bit is cleared.
Bit 0 VPOL - This bit selects the polarity of the incom-
ing vertical sync signal (VSYNC). If it is negative polarity,
clear this bit. Otherwise, set this bit to 1 to represent the pos-
itive V sync signal. After power on, this bit is cleared.
• NOTE: The registers located at column 19 of row 15
are reserved for the chip testing. In normal operation,
they should not be programmed anytime.
Bit 7-6 WH41, WH40 - It determines the shadow height
of the window 4 when the window shadowing function is
activated. Please refer to the following table for more
details where N is the actual line number of the shadowing.
Table 3. Shadow Width Setting
(WH41, WH40)
Shadow Height N
(unit in Line)
(0, 0) (0, 1) (1, 0) (1, 1)
2
4
6
8
MOTOROLA
(IV) Special Control Registers
Chip Configuration Register(Row16, Coln0)
7
6
5
4
3
2
1
0
CLR FSS INV FSW VE HE DE DIV
Bit 7 CLR - By writing “1” to this bit, all display memory
from Row 0 to Row 14 are all cleared but not affecting
Control registers..
MC141585
13
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