CDP6805E2CE 데이터 시트보기 (PDF) - InnovASIC, Inc
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CDP6805E2CE Datasheet PDF : 31 Pages
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IA6805E2
Microprocessor Unit
Bus Timing
VSS=0V, TA=TL to TH (Figure 19)
Num
Parameters
1 Cycle Time
2 Pulse Width, DS Low
3 Pulse Width, DS High
4 Clock Transition
8 RW_n
9 Non-Muxed Address Hold
11 RW_n Delay From DS Fall
16 Non-Muxed Address Delay From AS Rise
17 MPU Read Data Setup
18 Read Data Hold
19 MPU Data Delay, Write
21 Write Data Hold
23 Muxed Address Delay From AS Rise
24 Muxed Address Valid to AS Fall
25 Muxed Address Hold
26 Delay DS Fall to AS Rise
27 Pulse Width, AS High
28 Delay, AS Fall to DS Rise
Data Sheet
As of Production Version 00
VDD = 5.0V ±10%
fOSC = 5MHz
1 TTL, 100pF Load Unit
Min
Max
1000
DC
ns
587
-
ns
403
-
ns
-
4
ns
9
-
ns
97
-
ns
-
40
ns
-
11
ns
18
-
ns
0
ns
-
0
ns
204
-
ns
-
26
ns
185
-
ns
103
-
ns
190
-
ns
203
-
ns
185
-
ns
ADDRESS_STROBE
PORT_INPUT
PORT_OUTPUT
VLOW = 0.8V, VHIGH = VDD – 2.0V, VDD = 5.0V ±10%
TA = TL to TH, CL on Port = 50pF, fOSC = 5MHz
tPVASL
*NOTE
tASLPX
tASLPV
*Note: The address strobe of the first cycle of the next instruction.
Figure 14. I/O Port Timing
Copyright © 2002
innovASIC
The End of Obsolescence™
ENG21108140100
Page 25 of 31
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