MC33099 데이터 시트보기 (PDF) - Motorola => Freescale

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MC33099

ALTERNATOR VOLTAGE REGULATOR

Motorola => Freescale 

MC33099

Lamp polling is also present when the lamp is ON. In this

case, lamp polling turns OFF the lamp for a short period of

time with the lamp being ON for the remainder of the time. In

this case the lamp ON duty cycle is 98.44% (or OFF for

158uS) at a frequency of fmsb/4, or 98.6 Hz. This causes the

lamp voltage on the lamp drain terminal to be greater than

ignition threshold voltage VTign for at least 158 µS of a

10.1 mS period. During the lamp ON mode, the Ignition Turn

Off Delay of the Ignition Delay circuit is greater then the

10.1 mS period. As a result, the regulator biasing remains ON

even when the IGN terminal is coupled to the Lamp Drain

terminal and the lamp drain voltage is less than voltage VTign

most of the time when the lamp is ON.

The lamp driver is also protected from load dump, since

during load dump, the LD–bar signal is a logic 0, preventing

the AND2 gate from activating the lamp driver. In addition, a

drain to gate clamp device Z2 limits the drain to gate

clamping voltage (Vdg) to about 40 V typically.

Under Voltage, Over Voltage and Load Dump Protection

An undervoltage, over voltage and load dump condition is

sensed by the regulator to generate fault indications and to

protect the regulator and associated external devices. As

previously discussed, a load dump signal during load dump

will prevent Gate drive to the external MOSFET and prevent

gate drive to the lamp driver. Thus the external and internal

MOSFETs will turn OFF during a system load dump. As

previously discussed, the under voltage and over voltage

signals are also provided for fault indications.

The under voltage signal is provided on the UV line by an

under voltage comparator Cuv having a voltage reference of

1.25 V and a resistor divider voltage transfer of 1.26 from the

FB output to comparator Cuv input. When voltage Vfb on the

FB output becomes less than 1.52V, the voltage at input to

comparator Cuv becomes less than 1.25 V, causing

comparator Cuv to output an undervoltage UV signal. Since

voltage Vfb is ideally voltage Vrs (or voltage Vls), and the ratio

of Vr/Vrs (or Vl/Vls) is 7.45, the UV signal will occur when the

system voltage at the Remote input (or Local input) is less

than an undervoltage threshold voltage (VTuv), or 11.35 V.

However, Gate AND1 insures that frequency fph must be

greater than f2 before an under voltage Fault is indicated by

the lamp.

The load dump and over voltage detection also utilizes

similar resistor dividers and voltage comparators in an Over

Voltage Detect circuitry where all comparators are

referenced to voltage Vref, or about 2.0 V. When voltage Vfb

on the FB output is greater than 2.58V, or 1.29 Vref (Vfb/Vref =

1.29) an output load dump signal of a logic 0 is generated on

the LD–bar line. Thus during load dump, voltage Vrs (or

Vlocal) will be about 2.58 V, and the actual load dump

threshold voltage (VTld) will be about 19.25 V, or 1.3 Vset.

When voltage Vfb on the FB output is greater than 1.117 Vref

(Vfb/Vref = 1.117) an output over voltage signal is generated

on the OV line. Thus voltage Vrs (or Vl) will be about 2.235 V,

and the actual overvoltage threshold voltage (VTov) will be

about 16.65 V, or 1.125 Vset.

The regulator also indicates an over voltage condition on

the system during the Remote fault condition when the

remote wire resistance increases to a finite value and the

system voltage is being regulated by secondary regulation at

Vset2. When a load dump occurs during secondary

regulation, the load dump threshold increases to 1.3 Vset2, or

about 24 V.

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MOTOROLA ANALOG IC DEVICE DATA

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