MC68HC05L28 데이터 시트보기 (PDF) - Freescale Semiconductor

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MC68HC05L28

Microcontrollers

Freescale Semiconductor 

Freescale Semiconductor, Inc.

LIST OF FIGURES

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A-1

A-2

MC68HC05L28/MC68HC705L28 block diagram....................................................1-2

RAM bootloader circuit ...........................................................................................2-3

MC68HC705L28 EPROM programming circuit ......................................................2-5

Oscillator connections ............................................................................................2-7

RC connection for external POR ............................................................................2-8

STOP flowchart ......................................................................................................2-11

WAIT flowchart .......................................................................................................2-13

Memory map of the MC68HC05L28 and MC68HC705L28 ....................................3-2

Standard I/O port structure.....................................................................................4-2

Core timer block diagram........................................................................................5-1

16-bit programmable timer block diagram ..............................................................6-2

Timer state timing diagram for reset .......................................................................6-14

Timer state timing diagram for input capture ..........................................................6-14

Timer state timing diagram for output compare ......................................................6-15

Timer state timing diagram for timer overflow.........................................................6-15

LCD system block diagram.....................................................................................7-1

Voltage level selection ............................................................................................7-3

LCD waveform with 2 backplanes, 1/2 bias ............................................................7-4

LCD waveform with 2 backplanes, 1/3 bias ............................................................7-5

LCD waveform with 3 backplanes...........................................................................7-6

LCD waveform with 4 backplanes...........................................................................7-7

I2C bus transmission signal diagrams ....................................................................8-3

Clock synchronization.............................................................................................8-5

Example of a typical I2C-bus interrupt routine ........................................................8-14

A/D converter block diagram ..................................................................................9-2

Electrical model of an A/D input pin........................................................................9-6

Interrupt flow chart................................................................................................10-4

Programming model .............................................................................................11-1

Stacking order ......................................................................................................11-2

Equivalent test load ..............................................................................................12-2

56-pin SDIP pinout for the MC68HC05L28/MC68HC705L28...............................13-1

Mechanical dimensions for 56-pin SDIP...............................................................13-2

MC68HC705L28 EPROM programming circuit ..................................................... A-3

56-pin SDIP pinout for the MC68HC705L28.......................................................... A-6

MC68HC05L28

LIST OF FIGURES

TPG

MOTOROLA

vii

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