MIC4690
To minimize stray inductance and ground loops, keep trace
lengths, indicated by the heavy lines in Figure 5, as short as
possible. For example, keep D1 close to pin 3 and pins 5
through 8, keep L1 away from sensitive node FB, and keep
CIN close to pin 2 and pins 5 though 8. See “Applications
Information: Thermal Considerations” for ground plane lay-
out.
Micrel
The feedback pin should be kept as far way from the switching
elements (usually L1 and D1) as possible.
A circuit with sample layouts are provided. See Figures 6a
though 6e. Gerber files are available upon request.
+4V tVoIN+30V
(34V transients)
CIN
Power
SOP-8
MIC4690BM
2 VIN
SW 3
1 SHDN
FB 4
GND
5678
L1
D1
VOUT
COUT R1
R2
GND
Figure 5. Critical Traces for Layout
J1
4V toVI+N30V
(34V transients)
C1
22µF
35V
J3
GND
C2
0.1µF
OFF
50V
ON JP1
U1 MIC4690BM
2 IN
SW 3
1 SHDN
FB 4
GND
SOP-8 5Ð8
* C3 can be used to provide additional stability
and improved transient response.
L1
18µH
R1
3.01k
C3* 1800pF / 50V
optional
D1 R6
R2 R3 R4 R5
2A optional 6.49k 2.94k 1.78k 976½
40V
1 JP2a3 JP2b5 JP2c7 JP2d
1.8V 2.5V 3.3V 5.0V
2
4
6
8
Figure 6a. Evaluation Board Schematic Diagram
C4
220µF
10V
J2
V1OAUT
C5
0.1µF
50V
J4
GND
MIC4690
10
April 2005