ML7020 데이터 시트보기 (PDF) - Oki Electric Industry
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ML7020 Datasheet PDF : 19 Pages
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1Semiconductor
FEDL7020-02
ML7020
• MODE2 to MODE0
These registers are used for setting the mode. The contents of setting are shown in Table 3.
Table 3 List of mode settings
Operation of different blocks
MODE2 MODE1 MODE0 Mode name Modulator Demodulator DTMF
DTMF
CPT
CPT
section section transmission reception transmission reception
Modem
0
0
0 transmission
O
–
–
–
O
–
0
0
1
Modem
–
O
reception
–
–
O
–
Tone 1
0
1
0
–
–
(Note 1)
–
O
O
–
Tone 2
0
1
1
–
–
(Note 1)
O
O
O
O
Tone 3
1
0
0
–
–
(Note 1)
O
O
O
O
Loop back
1
0
1
O
O
(Note 2)
O
O
–
–
1
1
0
Test
LSI internal test
Power down
1
1
1
(Note 3)
–
–
–
–
–
–
*[O]: Operating condition, [–]: Power down condition
Note 1: Tone 1, 2, 3 modes
The DTMF detection timing is different in the tone 1, 2, loop back modes from that in the tone 3
mode.
In the tone 3 mode, the DTMF detection goes into the high speed detection mode. In this
mode, since the detector can make incorrect detection due to voice signals or noise, avoid
using the tone 3 mode if there is any margin available in the timing.
Note 2: Loop back mode
The modem loop back mode is initiated when SW5CONT is High and MOD-DT_ON is High.
(The data input in XD is output from RD via the internal circuits.)
The DTMF loop back mode is initiated when SW5CONT is Low and MOD-DT_ON is High.
(The data set in PBG3 to PBG0 is latched at the rising edge of MOD-DT_ON, and is output at
PBR3 to PBR0 via the internal circuits.)
Note 3: Power down mode
The conditions when the LSI is put in the power down mode are listed below.
Each blocks:
Stop operating and the internal circuits are reset.
Analog output pins:
Go to the high-impedance state
DETB, RD, CLKO pins:
High level
SP, X2 pins:
Low level
Processor interface registers:
Low level (excepting SW1CONT, MODE2, 1, 0)
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