OKI Semiconductor
~ PCM interface
PCMCLK(I)
PCMIN
PCMOUT
PCMSYNC(I)
FEDL7055-02
ML7055
Tpc2
Tpc3 Tpc4
Tpc0 Tpc1
Tpc2
Tpc3 Tpc4
PCMCLK(O)
PCMIN
PCMOUT
PCMSYNC(O)
Tpc 7
Tpc 8
Tpc5 Tpc6
Tpc7
Parameter
Tpc0
Tpc1
Tpc2
Tpc3
Tpc4
Tpc5
Tpc6
Tpc7
Tpc8
(Vdd = 2.7 to 3.6V, CoreVdd = 1.65 to 1.95V, Ta = -40 to 85°C)
Description
Min Typ Max Unit
PCMIN setup time relative to PCMCLK (input) falling edge 100 — — ns
PCMIN hold time relative to PCMCLK (input) falling edge
100 — — ns
PCMOUT delay time relative to PCMCLK (input) rising edge — — 250 ns
PCMSYNC (input) setup time relative to PCMCLK (input)
rising edge
100
—
—
ns
PCMSYNC (input) hold time relative to PCMCLK (input)
rising edge
100
—
—
ns
PCMIN setup time relative to PCMCLK (output) falling edge 100 — — ns
PCMIN hold time relative to PCMCLK (output) falling edge 100 — — ns
PCMOUT delay time relative to PCMCLK (output) rising
edge
—
—
250
ns
Delay time from PCMCLK (output) rising edge to PCMSYNC
(output)
—
—
150
ns
~ AC Characteristic Measuring Points
VDD
0V
0.8VDD
0.2VDD
0.8VDD
0.2VDD
19/30