MPC8540(2004) 데이터 시트보기 (PDF) - Freescale Semiconductor
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MPC8540 Datasheet PDF : 1302 Pages
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Contents
Paragraph
Number
Title
Page
Number
13.4.3.9
13.4.3.10
13.4.3.11
13.4.3.11.1
13.4.4
13.4.4.1
13.4.4.1.1
13.4.4.1.2
13.4.4.1.3
13.4.4.1.4
13.4.4.2
13.4.4.3
13.4.4.4
13.4.4.4.1
13.4.4.4.2
13.4.4.4.3
13.4.4.4.4
13.4.4.4.5
13.4.4.4.6
13.4.4.4.7
13.4.4.4.8
13.4.4.4.9
13.4.4.4.10
13.4.4.5
13.4.4.6
13.4.4.7
13.5
13.5.1
13.5.1.1
13.5.1.2
13.5.1.3
13.5.1.4
13.5.2
13.5.2.1
13.5.2.2
13.5.2.3
13.5.2.4
13.5.3
13.5.4
13.5.4.1
SDRAM Read/Write Transactions....................................................................... 13-60
SDRAM MODE-SET Command Timing............................................................ 13-60
SDRAM Refresh.................................................................................................. 13-61
SDRAM Refresh Timing ................................................................................. 13-61
User-Programmable Machines (UPMs)................................................................... 13-62
UPM Requests ..................................................................................................... 13-63
Memory Access Requests................................................................................ 13-64
UPM Refresh Timer Requests ......................................................................... 13-65
Software Requests—RUN Command ............................................................. 13-65
Exception Requests.......................................................................................... 13-66
Programming the UPMs ...................................................................................... 13-66
UPM Signal Timing............................................................................................. 13-66
RAM Array .......................................................................................................... 13-67
RAM Words..................................................................................................... 13-68
Chip-Select Signal Timing (CSTn) ................................................................. 13-72
Byte Select Signal Timing (BSTn) .................................................................. 13-72
General-Purpose Signals (GnTn, GOn)........................................................... 13-73
Loop Control (LOOP) ..................................................................................... 13-73
Repeat Execution of Current RAM Word (REDO) ......................................... 13-74
Address Multiplexing (AMX) ......................................................................... 13-74
Data Valid and Data Sample Control (UTA) ................................................... 13-75
LGPL[0:5] Signal Negation (LAST) ............................................................... 13-76
Wait Mechanism (WAEN) ............................................................................... 13-76
Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge ............ 13-77
Extended Hold Time on Read Accesses .............................................................. 13-77
Memory System Interface Example Using UPM ................................................ 13-78
Initialization/Application Information ......................................................................... 13-84
Interfacing to Peripherals......................................................................................... 13-84
Multiplexed Address/Data Bus and Unmultiplexed Address Signals ................. 13-84
Peripheral Hierarchy on the Local Bus................................................................ 13-84
Peripheral Hierarchy on the Local Bus for Very High Bus Speeds..................... 13-85
GPCM Timings.................................................................................................... 13-86
Bus Turnaround ....................................................................................................... 13-87
Address Phase After Previous Read .................................................................... 13-87
Read Data Phase After Address Phase ................................................................ 13-88
Read-Modify-Write Cycle for Parity Protected Memory Banks ......................... 13-88
UPM Cycles with Additional Address Phases..................................................... 13-88
Interface to Different Port-Size Devices.................................................................. 13-88
Interfacing to SDRAM............................................................................................. 13-90
Basic SDRAM Capabilities of the Local Bus...................................................... 13-90
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
xxi
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