MS81V04160A 데이터 시트보기 (PDF) - Oki Electric Industry

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MS81V04160A

Dual FIFO (262,214 Words × 8 Bits) × 2

Oki Electric Industry 

1Semiconductor

FEDS81V04160A-01

MS81V04160A

Read Cycle Timing (Read Enable): MODE1 = VCC/VSS, MODE2 =VCC

n cycle

Disable cycle Disable cycle

n + 1 cycle

VIH

SRCK

tREN

tRDSH

tRDSS

tRENS

VIL

RE1, 2

tWREL

DO

10-17/20-27

n–1

tWREH

n

VIH

VIL

VIH

n+1

VIL

VIH

OE1, 2

VIL

VIH

RSTR1, 2

VIL

Read Cycle Timing (Output Enable): MODE1 = VCC/VSS, MODE2 =VCC

n cycle

n + 1 cycle

n + 2 cycle

n + 3 cycle

VIH

SRCK

tOENH

tODSH

tODSS

tOENS

VIL

VIH

OE1, 2

tWOEL

VIL

tDECK

tWOEH

DO

10-17/20-27

n–1

n

Hi-Z

VIH

n+3

VIL

VIH

RE1, 2

VIL

VIH

RSTR1, 2

VIL

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