SLA24C64-S/P 데이터 시트보기 (PDF) - Infineon Technologies

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SLA24C64-S/P

64 Kbit (8192 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus

Infineon Technologies 

SLx 24C64

6.3 Sequential Read

A sequential read is initiated in the same way as a current read or a random read except

that the master acknowledges the data byte transmitted by the EEPROM. The EEPROM

then continues the data transmission. The internal address counter is incremented by

one during each data byte transmission.

A sequential read allows the entire memory to be read during one read operation. After

the highest addressable memory location is reached, the internal address pointer “rolls

over” to the address 0 and the sequential read continues.

The transmission is terminated by the master by releasing the SDA line (no

acknowledge) and generating a STOP condition (see figure 13).

S

T

S

Bus Activity A Command Byte

A

A

T

Master

R

CSR

C

C

O

T

K

K

P

SDA Line S

1

P

Bus Activity

EEPROM

A Data Byte n

C

K

Data Byte n+1 Data Byte n+x

IED02134

Figure 13

Sequential Read

Semiconductor Group

19

1999-02-02

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