RM5261A-300-HI 데이터 시트보기 (PDF) - PMC-Sierra

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RM5261A-300-HI

Microprocessor with 64-Bit System Bus

PMC-Sierra 

RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet

Preliminary

3.4 Pipeline

For integer operations, loads, stores, and other non-floating-point operations, the RM5261A

implements a 5-stage integer pipeline. In addition to the integer pipeline, the RM5261A

implements an extended 7-stage pipeline for floating-point operations.

The RM5261A multiplies the input SysClock by 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, or 9 to produce the

pipeline clock.

Figure 3 shows the RM5261A integer pipeline. As illustrated in the figure, up to five integer

instructions can be executing simultaneously.

Figure 3 Pipeline

I0 1I 2I 1R 2R 1A 2A 1D 2D 1W 2W

I1

1I 2I 1R 2R 1A 2A 1D 2D 1W 2W

I2

1I 2I 1R 2R 1A 2A 1D 2D 1W 2W

I3

1I 2I 1R 2R 1A 2A 1D 2D 1W 2W

I4

1I 2I 1R 2R 1A 2A 1D 2D 1W 2W

one cycle

1I-1R: Instruction cache access

2I: Instruction virtual to physical address translation

2R: Register file read, Bypass calculation, Instruction decode, Branch address calculation

1A: Issue or slip decision, Branch decision

1A: Data virtual address calculation

1A-2A: Integer add, logical, shift

2A: Store Align

2A-2D: Data cache access and load align

1D: Data virtual to physical address translation

2W: Register file write

3.5 Register File

The RM5261A has thirty-two general purpose registers with register location 0 (r0) hard-wired to

a zero value. These registers are used for scalar integer operations and address calculation. The

register file has two read ports and one write port and is fully bypassed to minimize operation

latency in the pipeline.

3.6 ALU

The RM5261A ALU consists of an integer adder/subtractor, a logic unit, and a shifter. The adder

performs address calculations in addition to arithmetic operations. The logic unit performs all

logical and zero shift data moves. The shifter performs shifts and store alignment operations. Each

of these units is optimized to perform all operations in a single processor cycle.

3.7 Integer Multiply/Divide

The RM5261A has a dedicated integer multiply/divide unit optimized for high-speed multiply and

multiply-accumulate operations. Table 1 shows the performance of the multiply/divide unit on

each operation.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

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Document ID: PMC-2002240, Issue 2

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