MT46H16M32LFB5-6C 데이터 시트보기 (PDF) - Micron Technology

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MT46H16M32LFB5-6C

Mobile Low-Power DDR SDRAM

Micron Technology 

512Mb: x16, x32 Mobile LPDDR SDRAM

Electrical Specifications

Table 5: AC/DC Electrical Characteristics and Operating Conditions (Continued)

Notes 1–5 apply to all parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V

Parameter/Condition

Symbol

Min

Output leakage current

(DQ are disabled; 0V ≤ VOUT ≤ VDDQ)

Operating temperature

IOZ

–5

Commercial

Industrial

Automotive

TA

0

TA

–40

TA

–40

Max

5

+70

+85

+105

Unit

μA

Notes

˚C

˚C

˚C

Notes:

1. All voltages referenced to VSS.

2. All parameters assume proper device initialization.

3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at

nominal supply voltage levels, but the related specifications and device operation are

guaranteed for the full voltage range specified.

4. Outputs measured with equivalent load; transmission line delay is assumed to be very

small:

50

I/O

50

I/O

20pF

10pF

Full drive strength

Half drive strength

5. Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment,

but input timing is still referenced to VDDQ/2 (or to the crossing point for CK/CK#). The

output timing reference voltage level is VDDQ/2.

6. Any positive glitch must be less than one-third of the clock cycle and not more than

+200mV or 2.0V, whichever is less. Any negative glitch must be less than one-third of the

clock cycle and not exceed either –150mV or +1.6V, whichever is more positive.

7. VDD and VDDQ must track each other and VDDQ must be less than or equal to VDD.

8. To maintain a valid level, the transitioning edge of the input must:

8a. Sustain a constant slew rate from the current AC level through to the target AC lev-

el, VIL(AC) Or VIH(AC).

8b. Reach at least the target AC level.

8c. After the AC target level is reached, continue to maintain at least the target DC lev-

el, VIL(DC) or VIH(DC).

9. VIH overshoot: VIHmax = VDDQ + 1.0V for a pulse width ≤3ns and the pulse width cannot

be greater than one-third of the cycle rate. VIL undershoot: VILmin = –1.0V for a pulse

width ≤3ns and the pulse width cannot be greater than one-third of the cycle rate.

10. CK and CK# input slew rate must be ≥1 V/ns (2 V/ns if measured differentially).

11. VID is the magnitude of the difference between the input level on CK and the input lev-

el on CK#.

12. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track

variations in the DC level of the same.

13. DQ and DM input slew rates must not deviate from DQS by more than 10%. 50ps must

be added to tDS and tDH for each 100 mV/ns reduction in slew rate. If slew rate exceeds

4 V/ns, functionality is uncertain.

PDF: 09005aef83dd2b3e

t67m_512mb_mobile_lpddr.pdf - Rev. H 06/13 EN

18

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2009 Micron Technology, Inc. All rights reserved.

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