MT46H16M32LF 데이터 시트보기 (PDF) - Micron Technology
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MT46H16M32LF Datasheet PDF : 96 Pages
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512Mb: x16, x32 Mobile LPDDR SDRAM
Electrical Specifications – IDD Parameters
Table 9: IDD Specifications and Conditions, –40°C to +105°C (x16)
Notes 1–5 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Max
Parameter/Condition
Symbol -5
-54
-6
Operating 1 bank active precharge current: tRC = tRC (MIN); tCK IDD0
70
65
60
= tCK (MIN); CKE is HIGH; CS is HIGH between valid commands;
Address inputs are switching every 2 clock cycles; Data bus in-
puts are stable
Precharge power-down standby current: All banks idle; CKE is
IDD2P
600
600
600
LOW; CS is HIGH; tCK = tCK (MIN); Address and control inputs
are switching; Data bus inputs are stable
Precharge power-down standby current: Clock stopped; All
IDD2PS
600
600
600
banks idle; CKE is LOW; CS is HIGH; CK = LOW, CK# = HIGH; Ad-
dress and control inputs are switching; Data bus inputs are sta-
ble
Precharge nonpower-down standby current: All banks idle;
IDD2N
16
16
16
CKE = HIGH; CS = HIGH; tCK = tCK (MIN); Address and control
inputs are switching; Data bus inputs are stable
Precharge nonpower-down standby current: Clock stopped; All IDD2NS
9
9
9
banks idle; CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Ad-
dress and control inputs are switching; Data bus inputs are sta-
ble
Active power-down standby current: 1 bank active; CKE = LOW; IDD3P
4
4
4
CS = HIGH; tCK = tCK (MIN); Address and control inputs are
switching; Data bus inputs are stable
Active power-down standby current: Clock stopped; 1 bank ac- IDD3PS
3
3
3
tive; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address
and control inputs are switching; Data bus inputs are stable
Active nonpower-down standby: 1 bank active; CKE = HIGH; CS IDD3N
16
16
16
= HIGH; tCK = tCK (MIN); Address and control inputs are switch-
ing; Data bus inputs are stable
Active nonpower-down standby: Clock stopped; 1 bank active; IDD3NS
9
9
9
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Operating burst read: 1 bank active; BL = 4; tCK = tCK (MIN);
Continuous READ bursts; Iout = 0mA; Address inputs are
switching every 2 clock cycles; 50% data changing each burst
IDD4R
115
110
105
Operating burst write: 1 bank active; BL = 4; tCK = tCK (MIN);
Continuous WRITE bursts; Address inputs are switching; 50%
data changing each burst
IDD4W
115
110
105
Auto refresh: Burst refresh; CKE = HIGH; Ad- tRFC = 138ns
IDD5
95
95
95
dress and control inputs are switching; Data
bus inputs are stable
tRFC = tREFI
IDD5A
8
8
8
Deep power-down current: Address and control balls are sta-
IDD8
15
15
15
ble; Data bus inputs are stable
-75 Unit Notes
50 mA 6
600 μA 7, 8
600 μA
7
13 mA 9
9 mA 9
4 mA 8
3 mA
16 mA 6
9 mA 6
100 mA 6
100 mA 6
95 mA 10
8 mA 10, 11
15 μA 7, 13
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. H 06/13 EN
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© 2009 Micron Technology, Inc. All rights reserved.
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