MT46H16M32LF 데이터 시트보기 (PDF) - Micron Technology

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MT46H16M32LF

Mobile Low-Power DDR SDRAM

Micron Technology 

512Mb: x16, x32 Mobile LPDDR SDRAM

Electrical Specifications – IDD Parameters

Table 11: IDD6 Specifications and Conditions

Notes 1–5, 7, and 12 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–

1.95V

Parameter/Condition

Symbol Standard Unit

Self refresh

Full array, 105˚C

IDD6

CKE = LOW; tCK = tCK (MIN); Address

Full array, 85°C

and control inputs are stable; Data bus

inputs are stable

Full array, 45˚C

1/2 array, 85˚C

n/a14

μA

700

µA

390

μA

520

μA

1/2 array, 45˚C

310

μA

1/4 array, 85˚C

430

μA

1/4 array, 45˚C

275

μA

1/8 array, 85˚C

430

μA

1/8 array, 45˚C

275

μA

1/16 array, 85˚C

375

μA

1/16 array, 45˚C

250

μA

Notes:

1. All voltages referenced to VSS.

2. Tests for IDD characteristics may be conducted at nominal supply voltage levels, but the

related specifications and device operation are guaranteed for the full voltage range

specified.

3. Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment,

but input timing is still referenced to VDDQ/2 (or to the crossing point for CK/CK#). The

output timing reference voltage level is VDDQ/2.

4. IDD is dependent on output loading and cycle rates. Specified values are obtained with

minimum cycle time with the outputs open.

5. IDD specifications are tested after the device is properly initialized and values are aver-

aged at the defined cycle rate.

6. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the

minimum absolute value for the respective parameter. tRASmax for IDD measurements is

the largest multiple of tCK that meets the maximum absolute value for tRAS.

7. Measurement is taken 500ms after entering into this operating mode to provide settling

time for the tester.

8. VDD must not vary more than 4% if CKE is not active while any bank is active.

9. IDD2N specifies DQ, DQS, and DM to be driven to a valid high or low logic level.

10. CKE must be active (HIGH) during the entire time a REFRESH command is executed.

From the time the AUTO REFRESH command is registered, CKE must be active at each

rising clock edge until tRFC later.

11. This limit is a nominal value and does not result in a fail. CKE is HIGH during REFRESH

command period (tRFC (MIN)) else CKE is LOW (for example, during standby).

12. Values for IDD6 85˚C are guaranteed for the entire temperature range. All other IDD6 val-

ues are estimated.

13. Typical values at 25˚C, not a maximum value.

14. Self refresh is not supported for AT (85°C to 105°C) operation.

PDF: 09005aef83dd2b3e

t67m_512mb_mobile_lpddr.pdf - Rev. H 06/13 EN

24

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2009 Micron Technology, Inc. All rights reserved.

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