MT46H16M16 데이터 시트보기 (PDF) - Micron Technology

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MT46H16M16

Mobile DDR SDRAM

Micron Technology 

256Mb: x16, x32 Mobile DDR SDRAM

Commands

Commands

Tables 7 and 8 provide a quick reference of available commands. This is followed by a

description of each command. Three additional truth tables provide CKE commands

and current/next state information (see Table 9 on page 51, Table 10 on page 52, and

Table 11 on page 54).

Table 7:

Truth Table – Commands

Notes 1 and 2 apply to all commands

Name (Function)

DESELECT (NOP)

NO OPERATION (NOP)

ACTIVE (select bank and activate row)

READ (select bank and column, and start READ burst)

WRITE (select bank and column, and start WRITE burst)

BURST TERMINATE or deep power-down

(enter deep power-down mode)

PRECHARGE (deactivate row in bank or banks)

AUTO REFRESH (refresh all or single bank) or

SELF REFRESH (enter self refresh mode)

LOAD MODE REGISTER (standard or extended mode

registers)

CS# RAS# CAS# WE#

H

X

X

X

L

H

H

H

L

L

H

H

L

H

L

H

L

H

L

L

L

H

H

L

L

L

H

L

L

L

L

H

L

L

L

L

Address

X

X

Bank/row

Bank/column

Bank/column

X

Code

X

Op-code

Notes

3

3

4

5

5

6, 7

8

9, 10

11

Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH and deep power-down.

2. All states and sequences not shown are reserved and/or illegal.

3. DESELECT and NOP are functionally interchangeable.

4. BA0–BA1 provide bank address and A0–A12/A13 provide row address.

5. BA0–BA1 provide bank address; A0–A8 provide column address; A10 HIGH enables the auto

precharge feature (nonpersistent); A10 LOW disables the auto precharge feature.

6. Applies only to read bursts with auto precharge disabled; this command is undefined (and

should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.

7. This command is a BURST TERMINATE if CKE is HIGH and deep power-down if CKE is LOW.

8. A10 LOW: BA0–BA1 determine which bank is precharged.

A10 HIGH: all banks are precharged and BA0–BA1 are “Don’t Care.”

9. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

10. Internal refresh counter controls row addressing; all self refresh inputs and I/Os are “Don’t

Care” except for CKE.

11. BA0–BA1 either select the standard mode register or the extended mode register

(BA0 = 0, BA1 = 0 select the standard mode register; BA0 = 0, BA1 = 1 select extended mode

register; other combinations of BA0–BA1 are reserved). A0–A12/A13 provide the op-code to

be written to the selected mode register.

Table 8: Truth Table – DM Operation

Name (Function)

Write enable

Write inhibit

DM

DQ

Notes

L

Valid

1, 2

H

X

1, 2

Notes: 1. Used to mask write data; provided coincident with the corresponding data.

2. All states and sequences not shown are reserved and illegal.

PDF: 09005aef82091978 / Source: 09005aef8209195b

MT46H16M16LF__2.fm - Rev. H 6/08 EN

22

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2005 Micron Technology, Inc. All rights reserved.

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