MT41J128M 데이터 시트보기 (PDF) - Micron Technology
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MT41J128M Datasheet PDF : 214 Pages
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1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications
Input/Output Capacitance
Table 7: DDR3 Input/Output Capacitance
Note 1 applies to the entire table
Capacitance
Parameters
800
1066
1333
1600
1866
2133
Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Notes
CK and CK#
ΔC: CK to CK#
Single-end I/O:
DQ, DM
CCK
0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 0.8 1.3 pF
CDCK
0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF
CIO
1.5 3.0 1.5 2.7 1.5 2.5 1.5 2.3 1.5 2.2 1.5 2.1 pF
2
Differential I/O:
CIO
1.5 3.0 1.5 2.7 1.5 2.5 1.5 2.3 1.5 2.2 1.5 2.1 pF 3
DQS, DQS#,
TDQS, TDQS#
ΔC: DQS to
DQS#, TDQS,
TDQS#
CDDQS
0 0.2 0 0.2 0 0.15 0 0.15 0 0.15 0 0.15 pF
3
ΔC: DQ to DQS
Inputs (CTRL,
CMD, ADDR)
CDIO –0.5 0.3 –0.5 0.3 –0.5 0.3 –0.5 0.3 –0.5 0.3 –0.5 0.3 pF
4
CI
0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pF
5
ΔC: CTRL to CK CDI_CTRL –0.5 0.3 –0.5 0.3 –0.4 0.2 –0.4 0.2 –0.4 0.2 –0.4 0.2 pF
6
ΔC: CMD_ADDR CDI_CMD_ –0.5 0.5 –0.5 0.5 –0.4 0.4 –0.4 0.4 –0.4 0.4 –0.4 0.4 pF
7
to CK
ADDR
ZQ pin capaci-
tance
CZQ
– 3.0 – 3.0 – 3.0 – 3.0 – 3.0 – 3.0 pF
Reset pin capaci- CRE
tance
– 3.0 – 3.0 – 3.0 – 3.0 – 3.0 – 3.0 pF
Notes:
1. VDD = 1.5V ±0.075mV, VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25°C. VOUT(DC) = 0.5 ×
VDDQ, VOUT = 0.1V (peak-to-peak).
2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. CDDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately.
4. CDIO = CIO(DQ) - 0.5 × (CIO(DQS) + CIO(DQS#)).
5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =
A[n:0], BA[2:0].
6. CDI_CTRL = CI(CTRL) - 0.5 × (CCK(CK) + CCK(CK#)).
7. CDI_CMD_ADDR = CI(CMD_ADDR) - 0.5 × (CCK(CK) + CCK(CK#)).
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
31
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
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