MT48H16M16LFBF-8 데이터 시트보기 (PDF) - Micron Technology
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MT48H16M16LFBF-8 Datasheet PDF : 71 Pages
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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Functional Description
Functional Description
In general, a 256Mb SDRAM is quad-bank DRAM that operates at 1.8V and includes a
synchronous interface (all signals are registered on the positive edge of the clock signal,
CLK).
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A12 select the row for x16, and A0–A11 select the row for x32). The
address bits (A0–A8 for x16 and A0–A8 for x32) registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
Initialization
SDRAM must be powered up and initialized in a predefined manner. Operational proce-
dures other than those specified may result in undefined operation. The initialization for
mobile SDRAM is as follows.
1. Simultaneously apply power to VDD and VDDQ.
2. After power supplies have settled, apply a stable clock signal. Stable clock is defined as
a signal cycling within timing constraints specified for the clock pin.
3. Wait at least 100µs. During this period NOP or COMMAND INHIBIT commands
should be applied. No other command other than NOP or COMMAND INHIBIT is
allowed during this period.
4. Preform a PRECHARGE ALL command to place the SDRAM into an all banks idle
state.
5. Wait at least tRP time. During this time NOP or COMMAND INHIBIT commands must
be applied.
6. Issue an AUTO REFRESH command.
7. Wait at least tRFC time, during which only NOP or COMMAND INHIBIT commands
are allowed.
8. Issue an Auto Refresh command.
9. Wait at least tRFC time, during which only NOP or COMMAND INHIBIT commands
are allowed.
10. Issue a LOAD MODE REGISTER command with BA1=0, andBA0=0, to program the
mode register with desired values.
11. Wait tMRD time. Only NOP or COMMAND INHIBIT commands may be applied dur-
ing this time.
12. Issue a LOAD MODE REGISTER command with BA1=1, and BA0=0, to program the
extended mode register with desired values.
13. Wait tMRD time. Only NOP or COMMAND INHIBIT commands may be applied dur-
ing this time.
The Mobile SDRAM is now initialized and can accept any valid command.
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
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©2006 Micron Technology, Inc. All rights reserved.
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