MT48H16M16LFBF-75 데이터 시트보기 (PDF) - Micron Technology
부품명
상세내역
제조사
MT48H16M16LFBF-75 Datasheet PDF : 71 Pages
| |||
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Register Definition
Register Definition
Mode Register
Burst Length (BL)
Burst Type
There are two MRs in the component: mode register and extended mode register (EMR).
The mode register is illustrated in Figure 6 on page 14. The mode register is used to
define the specific mode of operation of the SDRAM. This definition includes the selec-
tion of a burst length (BL), a burst type, a CAS latency (CL), an operating mode and a
write burst mode, as shown in Figure 6 on page 14. The mode register is programmed via
the LMR command and will retain the stored information until it is programmed again
or the device loses power.
M0–M2 mode register bits specify the BL, M3 specifies the type of burst, M4–M6 specify
the CL, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and
M10 and M11 should be set to zero.
The mode register must be loaded when all banks are idle, and the controller must wait
tMRD before initiating the subsequent operation. Violating either of these requirements
will result in unspecified operation.
Read and write accesses to the SDRAM are burst oriented, with the BL being program-
mable, as shown in Figure 6 on page 14. The BL determines the maximum number of
column locations that can be accessed for a given READ or WRITE command. BL = 1, 2,
4, 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the BL is effec-
tively selected. All accesses for that burst take place within this block, meaning that the
burst will wrap within the block if a boundary is reached. The block is uniquely selected
by A1–A8 when BL = 2, A2–A8 when BL = 4, and A3–A8 when BL = 8. The remaining (least
significant) address bit(s) is (are) used to select the starting location within the block.
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the BL, the burst type, and the
starting column address, as shown in Table 4 on page 15.
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Share Link: 