MT48H16M16LFBF-8G 데이터 시트보기 (PDF) - Micron Technology

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MT48H16M16LFBF-8G

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Micron Technology 

Figure 7: CAS Latency

CLK

COMMAND

DQ

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Register Definition

T0

T1

READ

NOP

tLZ

tAC

CL = 2

T2

T3

NOP

tOH

DOUT

CLK

COMMAND

T0

READ

DQ

T1

T2

NOP

NOP

tLZ

tAC

CL = 3

T3

T4

NOP

tOH

DOUT

DON’T CARE

UNDEFINED

Operating Mode

Write Burst Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other combi-

nations of values for M7 and M8 are reserved for future use.

Reserved states should not be used as unknown operation or incompatibility with future

versions may result.

When M9 = 0, the BL programmed via M0–M2 applies to both READ and WRITE bursts;

when M9 = 1, the programmed BL applies to READ bursts, but write accesses are single-

location accesses.

Extended Mode Register (EMR)

The low-power EMR controls the functions beyond those controlled by the MR. These

additional functions are special features of the mobile device. They include tempera-

ture-compensated self refresh (TCSR) control, partial-array self refresh (PASR), and

output drive strength.

The low-power EMR is programmed via the MODE REGISTER SET command and

retains the stored information until it is programmed again or the device loses power.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd

MT48H16M16LF_2.fm - Rev F 4/07 EN

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2006 Micron Technology, Inc. All rights reserved.

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