MT48H16M16LFB5-75 데이터 시트보기 (PDF) - Micron Technology

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MT48H16M16LFB5-75

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Micron Technology 

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Register Definition

Partial-Array Self Refresh (PASR)

For further power savings during self refresh, the partial-array self refresh (PASR) feature

allows the controller to select the amount of memory that will be refreshed during self

refresh. The following refresh options are available.

1. All banks (banks 0, 1, 2, and 3).

2. Two banks (banks 0 and 1; BA1=0).

3. One bank (bank 0; BA1 = BA0 = 0).

4. Half bank (bank 0; BA1 = BA0 = row address MSB = 0).

5. Quarter bank (bank 0; BA1 = BA0; row address MSB = row address MSB -1 = 0).

WRITE and READ commands occur to any bank selected during standard operation, but

only the selected banks in PASR will be refreshed during self refresh. It is important to

note that data in banks 2 and 3 will be lost when the two-bank option is used.

Driver Strength

Bits E5 and E6 of the EMR can be used to select the driver strength of the DQ outputs.

This value should be set according to the application’s requirements.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd

MT48H16M16LF_2.fm - Rev F 4/07 EN

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2006 Micron Technology, Inc. All rights reserved.

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