MT9123 데이터 시트보기 (PDF) - Mitel Networks
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MT9123 Datasheet PDF : 32 Pages
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Preliminary Information
MT9123
Register Summary
Echo Canceller A, Control Register 1
ADDRESS = 00h WRITE/READ VERIFY
CRA1
Reset INJDis BBM PAD Bypass AdaptDis
7
6
5
4
3
2
Echo Canceller B, Control Register 1
Extended
0 Delay
Power Reset Value
0000 0000
1
0
ADDRESS = 20h WRITE/READ VERIFY
CRB1
Extended-
Delay
AdaptDis
Bypass
PAD
BBM
INJDis
Reset
Reset INJDis BBM PAD Bypass AdaptDis 1
0
Power Reset Value
0000 0010
7
6
5
4
3
2
1
0
When high, Echo Cancellers A and B are internally cascaded into one 128ms echo canceller.
When low, Echo Cancellers A and B operate independently.
Do not enable both Extended-Delay and BBM configurations at the same time.
When high, echo canceller adaptation is disabled.
When low, the echo canceller dynamically adapts to the echo path characteristics.
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout.
When low, output data on both Sout and Rout is a function of the echo canceller algorithm.
When high, 12dB of attenuation is inserted into the Rin to Rout path.
When low the Rin to Rout path gain is 0dB.
When high the Back to Back configuration is enabled.
When low the Normal configuration is enabled. Do not enable Extended-Delay and BBM configurations at the same time.
Always set both BBM bits of the two echo cancellers to the same logic value to avoid conflict.
When high, the noise injection process is disabled. When low noise injection is enabled.
When high, the power-up initialization is executed presetting all register bits including this bit.
Note: Bits marked as “1” or “0” are reserved bits and should be written as indicated.
Echo Canceller A, Control Register 2
Echo Canceller B, Control Register 2
ADDRESS = 01h WRITE/READ VERIFY
ADDRESS = 21h WRITE/READ VERIFY
CR2
MuteR
MuteS
HPFDis
NBDis
NLPDis
0
0 NLPDis
0 NBDis HPFDis MuteS MuteR
Power Reset Value
0000 0000
7
6
5
4
3
2
1
0
When high, data on Rout is muted to quiet code. When low, Rout carries active code.
When high, data on Sout is muted to quiet code. When low, Sout carries active code.
When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths.
When low, the offset nulling filters are active and will remove DC offsets on PCM input signals.
When high, the narrow-band detector is disabled. When low, the narrow-band detector is enabled.
When high, the non-linear processor is disabled.
When low, the non-linear processors function normally. Useful for G.165 conformance testing.
Note: Bits marked as “0” are reserved bits and should be written as indicated.
Echo Canceller A, Status Register
Echo Canceller B, Status Register
ADDRESS = 02h READ
ADDRESS = 22h READ
SR
DTDet Conv Down Active
NB
Power Reset Value
0000 0000
NB
Active
Down
Conv
DTDet
7
6
5
4
3
2
1
0
Logic high indicates the presence of a narrow-band signal on Rin.
Logic high indicates that the power level on Rin is above the threshold level (i.e., low power condition).
Decision indicator for the non-linear processor gain adjustment.
Decision indicator for rapid adaptation convergence. Logic high indicates a rapid convergence state.
Logic high indicates the presence of a double-talk condition.
8-61
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