MT9162AN1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9162AN1

ISO2-CMOS 5 Volt Single Rail Codec

Zarlink Semiconductor Inc 

MT9162

Data Sheet

tR

CLOCKin 70%

(BCL)

30%

70%

Din

30%

70%

Dout

30%

tDOZL

tDOZH

70%

STB

30%

tBCLH

tBCL

tF

tBCLL

tDIS

tDIH

tSSS

tDD

tENW

tSSH

NOTE: Levels refer to% VDD (CMOS I/O)

Figure 5 - SSI Synchronous Timing Diagram

tDOLZ

tDOHZ

AC Electrical Characteristics† - SSI BUS Asynchronous Timing (note 1) (see Figure 6)

Characteristics

Sym.

Min.

Typ.‡

Max. Units

Test Conditions

1 Bit Cell Period

TDATA

2 Frame Jitter

Tj

3 Bit 1 Dout Delay from STB going tdda1

high

4 Bit 2 Dout Delay from STB going tdda2

high

5 Bit n Dout Delay from STB going tddan

high

600+

TDATA-Tj

600 +

(n-1) x

TDATA-Tj

7812

3906

600

Tj+600

600+

TDATA

600 +

(n-1) x

TDATA

600 +

TDATA+Tj

600 +

(n-1) x

TDATA+Tj

ns BCL=128 kHz

ns BCL=256 kHz

ns

ns CL=150 pF, RL=1K

ns CL=150 pF, RL=1K

ns CL=150 pF, RL=1K

n=3 to 8

6 Bit 1 Data Boundary

7 Din Bit n Data Setup time from

STB rising

8 Din Data Hold time from STB

rising

TDATA1

tSU

tho

TDATA-Tj

TDATA\2

+500ns-Tj

+(n-1) x

TDATA

TDATA\2

+500ns+Tj

+(n-1) x

TDATA

TDATA+Tj

ns

ns n=1-8

ns

† Timing is over recommended temperature range & recommended power supply voltages.

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

12

Zarlink Semiconductor Inc.

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