MT9171AN1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9171AN1

Integrated Digital Phone Circuit

Zarlink Semiconductor Inc 

MT9171/72

Data Sheet

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

Reg Sel-1 Reg Sel-2

Loopback

FUN

PSWAP

DLO

Default Mode Selection

(Refer to Table 4a)

Not Used

Bit

Name

Description

4

FUN1

Force Unsync. When set to ’1’, the DNIC is forced out-of-sync to test the SYNC

recovery circuitry. When set to ’0’, the operation continues in synchronization.

5

PSWAP1

Polynomial Swap. When set to ’1’, the scrambling and descrambling polynomials

are interchanged (use for MAS mode only). When set to ’0’, the polynomials retain

their normal designations.

6

DLO1

Disable Line Out. When set to ’1’, the signal on LOUT is set to VBias. When set to ’0’,

LOUT pin functions normally.

7

Not Used

Must be set to ’0’ for normal operation.

Table 5 - Diagnostic Register

Notes:

1. When bits 4-7 of the Diagnostic Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,

depending upon the status of bit-3.

2. Do not use LOUT to LIN loopback in DN/SLV mode.

3. Do not use DSTo to DSTi loopback in MOD/MAS mode.

The Diagnostics Register Reset bit (bit 2) of the Control Register determines the reset state of the Diagnostics

Register. If, on writing to the Control Register, this bit is set to logic “0”, the Diagnostics Register will be reset

coincident with the frame pulse. When this bit is logic “1”, the Diagnostics Register will not be reset. In order to use

the diagnostic features, the Diagnostics Register must be continuously written to. The output C-channel sends

status information from the Status Register to the system along with the received HK bit as shown in Table 6.

0

1

2

3

4

5

6

7

SYNC

CHQual

Rx HK

Future Functionality

ID

Status

Register

0

1-2

3

4-6

7

Name

Function

SYNC Synchronization - When set this bit indicates that synchronization to the received

line data sync pattern has been acquired. For DN mode only.

CHQual Channel Quality - These bits provide an estimate of the receiver’s margin against

noise. The farther this 2 bit value is from 0 the better the SNR.

Rx HK Housekeeping - This bit is the received housekeeping (HK) bit from the far end.

Future Future Functionality. These bits return Logic 1 when read.

ID This bit provides a hardware identifier for the DNIC revision. The MT9171/72 will

return a logic “0” for this bit. (Logic “1” returned for MT8972A.)

Table 6 - Status Register

13

Zarlink Semiconductor Inc.

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