MT9172AN1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9172AN1

Integrated Digital Phone Circuit

Zarlink Semiconductor Inc 

MT9171/72

Data Sheet

AC Electrical Characteristics† - Clock Timing - MOD Mode (Figure 18)

Characteristics

Sym.

80 kbit/s

Min. Typ.*

160 kbit/s

Max. Min. Typ.*

Max.

Units

Test

Conditions

1 TCK/RCK Clock Period

tCP

2 TCK/RCK Clock Width

tCW

12.5

6.25

6.25

3.125

3 TCK/RCK Clock Transition

tCT

20

20

Time

4 CLD to TCK Setup Time

tCLDS

3.125

1.56

5 CLD to TCK Hold Time

tCLDH

3.125

1.56

6 CLD Width Low

tCLDW

6.05

2.925

7 CLD Period

tCLDP

8xtCP

8xtCP

† Timing is over recommended temperature & power supply voltage ranges.

* Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing.

ms

ms

ns CL=40pF

ms

ms

ms

ms

2.4V

RCK

0.4V

2.4V

TCK

0.4V

2.4V

CLD

0.4V

tCLDS

tCLDH

tCLDW

tCP

tCW

tCT

tCP

tCW

tCT

Note 1:

Note 2:

TCK and CLD are generated on chip and provide the data clocks for the CD port and the transmit section of the

DV port. RCK, also generated on chip, is extracted from the receive data and only clocks out the data at the Do output

and may be skewed with respect to TCK due to end-to-end delay.

At the slave end TCK is phase locked to RCK.

The rising edge of TCK will lead the rising edge of RCK by approximately 90o.

Figure 18 - RCK, TCK & CLD Timing For MOD Mode

21

Zarlink Semiconductor Inc.

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