MT9172AN1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9172AN1

Integrated Digital Phone Circuit

Zarlink Semiconductor Inc 

MT9171/72

Data Sheet

Pin Description (continued)

Pin #

22 24 28

Name

Description

9 10

10 11

11 12

12 13

13 14

12 CDSTi/ Control/Data ST-BUS In/Control/Data In (Digital). A 2.048 Mbit/s serial control

CDi & signalling input in DN mode. In MOD mode this is a continuous bit stream at

the bit rate selected.

13 CDSTo/ Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048 Mbit/s serial

CDo control & signalling output in DN mode. In MOD mode this is a continuous bit

stream at the bit rate selected.

14

VSS Negative Power Supply (0 V).

15 DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048 Mbit/s serial PCM/data output in

DN mode. In MOD mode this is a continuous bit stream at the bit rate selected.

16 DSTi/Di Data ST-BUS In/Data In (Digital). A 2.048 Mbit/s serial PCM/data input in DN

mode. In MOD mode this is a continuous bit stream at the bit rate selected.

14 15

17 F0o/RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns

wide negative pulse indicating the end of the active channel times of the device

to allow daisy chaining. In MOD mode provides the receive bit rate clock to the

system.

15 16

16 17

17 19

18 20

8,

18

19 21

20 22

21 23

22 24

19 C4/TCK Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible

clock input for the MASTER and output for the SLAVE in DN mode. For MOD

mode this pin provides the transmit bit rate clock to the system.

21 OSC2 Oscillator Output. CMOS Output.

22 OSC1 Oscillator Input. CMOS Input. D.C. couple signals to this pin. Refer to D.C.

Electrical Characteristics for OSC1 input requirements.

23 Precan Precanceller Disable. When held to Logic ’1’, the internal path from LOUT to the

precanceller is forced to VBias thus bypassing the precanceller section. When

logic ’0’, the LOUT to the precanceller path is enabled and functions normally. An

internal pulldown (50 kΩ) is provided on this pin.

1,6,

NC No Connection. Leave open circuit

11,

18,

20,

25

24 LOUT DIS LOUT Disable. When held to logic “1”, LOUT is disabled (i.e., output = VBias). When

logic “0”, LOUT functions normally. An internal pulldown (50 kΩ) is provided on

this pin.

26 TEST Test Pin. Connect to VSS.

27

LIN Receive Signal input (Analog).

28

VDD Positive Power Supply (+5 V) input.

3

Zarlink Semiconductor Inc.

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