SPT7871SCU 데이터 시트보기 (PDF) - Signal Processing Technologies
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SPT7871SCU Datasheet PDF : 8 Pages
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TTL DIGITAL OUTPUT LEVELS
The SPT7871 supports TTL and some CMOS logic levels.
(Refer to minimum high voltage level for selected digital parts
that will interface with the SPT7871.) It has single-ended outputs
that are driven off a separate +5 V digital supply (DVCC).
THERMAL MANAGEMENT
SPT recommends that a heat sink be used for this device to
ensure rated performance. A heat sink in still air provides
Figure 2 - Typical Interface Circuit
Analog
Input
ECL
Differential
Clock Input
-A5.2
+A5
FB2
FB3
.01
.01
.01
X
X
**
VEE AGND AVCC
.01
DGND DVCC
D10
VIN
D9
D8
VT
D7
D6
VM
SPT7871
D5
D4
VB
D3
D2
D1
CLK
D0
CLK
MINV LINV
Interfacing
Logics
FB1
Notes:
1) X = Line termination
2) * = 0.01 µF chip cap. in parallel with
2.2 µF, tant cap.
+A5
+A5
10µF
+
-A5.2
10 µF
+
3) Immediate output buffer is highly recommended
to optimize the performance due to reflection. +5 V
AGND
-5.2 V
+D5
+D5
10 µF
+
DGND
+5V
adequate thermal performance under laboratory tests. Air
flow may be required for operation at elevated ambient
temperature. SPT recommends that the junction tempera-
ture be maintained under +150 °C.
The thermal impedance values for the cerquad package are
θJC = 3.3 °C/W and θJA = 70 °C/W (junction to ambient in still
air with no heat sink).
Figure 3 - Clock Input Equivalent Circuit
AVCC
(ESD)
26 kΩ
CLK
AGND
(ESD)
(ESD)
6 kΩ
26 kΩ
-1.3 V
52 kΩ
NCLK
(ESD)
VEE
Figure 4 - Digital Outputs Equivalent Circuit
DVCC
(ESD)
DGND
TTL OUT
(ESD)
44
C
1
D
AB
PACKAGE OUTLINE
44L Cerquad
SYMBOL
A
B
C
D
E
F
G
H
INCHES
MIN
MAX
0.550 typ
0.685
0.709
0.037
0.041
0.016 typ
0.008 typ
0.027
0.051
0.006 typ
0.080
0.150
MILLIMETERS
MIN
MAX
13.97 typ
17.40
18.00
0.94
1.04
0.41 typ
0.20 typ
0.69
1.30
0.15 typ
2.03
3.81
A
B
SPT
0 - 5°
E
7
H
G
F
SPT7871
9/7/98
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