AMIS-30522(2009) 데이터 시트보기 (PDF) - ON Semiconductor
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AMIS-30522 Datasheet PDF : 29 Pages
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AMIS−30522, NCV70522
VBB
VDD
tPU
VDDH
POR/WD pin
tPOR
tDSPI
Enable WD
> tWDPR and < tWDTO
Acknowledge WD
t
tWDTO
t
t
tWDRD
tPOR
= tWDPR or = tWDTO
WD timer
t
Figure 16. Watchdog Timing Diagram
Note: tDSPI is the time needed by the external
microcontroller to shift−in the <WDEN> bit after a
power−up.
The duration of the watchdog timeout interval is
programmable through the WDT[3:0] bits. The timing is
given in Figure 16.
CLR Pin (=Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip.
To reset the complete digital inside the 522, the input CLR
needs to be pulled to logic 1 during minimum time given by
tCLR. (See AC Parameters) This reset function clears all
internal registers without the need of a power−cycle, except
in sleep mode. The operation of all analog circuits is
depending on the reset state of the digital, charge pump
remains active. Logic 0 on CLR pin resumes normal
operation again. The voltage regulator remains functional
during and after the reset and the POR/WD pin is not
activated. Watchdog function is reset completely.
Sleep Mode
The bit <SLP> in SPI Control Register 2 is provided to
enter a so−called “sleep mode”. This mode allows reduction
of current−consumption when the motor is not in operation.
The effect of sleep mode is as follows:
• The drivers are put in HiZ
• All analog circuits are disabled and in low−power mode
• All internal registers are maintaining their logic content
• NXT and DIR inputs are ignored
• SPI communication remains possible (slight current
increase during SPI communication)
• Oscillator and digital clocks are silent, except during
SPI communication
Normal operation is resumed after writing logic ‘0’ to bit
<SLP>. A start−up time is needed for the charge pump to
stabilize. After this time, NXT commands can be issued.
When the device is in sleep mode and VBB becomes lower
than VBB_min the device might reset.
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