NLSX5012(2010) 데이터 시트보기 (PDF) - ON Semiconductor

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NLSX5012
(Rev.:2010)

2-Bit 100 Mb/s Configurable Dual-Supply Level Translator

ON Semiconductor 

NLSX5012

VL

Source

NLSX5012

EN

I/O VL

VCC

I/O VCC

CIOVCC

I/O VL

90%

50%

10%

I/O VCCtPD_VL−VCC

90%

50%

10%

tRISE/FALL v

3 ns

tF−VCC

tPD_VL−VCC

tR−VCC

Figure 7. Driving I/O VL Test Circuit and Timing

VL

I/O VL

CIOVL

NLSX5012

EN

I/O VCC

90%

50%

10%

I/O VLtPD_VCC−VL

90%

50%

10%

tRISE/FALL v 3 ns

tF−VL

VCC

I/O VCC

Source

tPD_VCC−VL

tR−VL

Figure 8. Driving I/O VCC Test Circuit and Timing

PULSE

GENERATOR

VCC

DUT

RT

R1

CL

RL

2xVCC

OPEN

Test

Switch

tPZH, tPHZ

Open

tPZL, tPLZ

2 x VCC

CL = 15 pF or equivalent (Includes jig and probe capacitance)

RL = R1 = 50 kW or equivalent

RT = ZOUT of pulse generator (typically 50 W)

Figure 9. Test Circuit for Enable/Disable Time Measurement

tR

Input

tPLH

Output

90%

50%

10%

90%

50%

10%

tR

tF

VCC

GND

tPHL

tF

EN

Output

Output

50%

tPZL tPLZ

50%

tPZH tPHZ

50%

VL

10%

90%

GND

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

Figure 10. Timing Definitions for Propagation Delays and Enable/Disable Measurement

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