SPT5230 데이터 시트보기 (PDF) - Signal Processing Technologies
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SPT5230 Datasheet PDF : 7 Pages
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INTERFACE CONSIDERATIONS
Figure 4 shows a typical interface circuit of the SPT5230 in
normal circuit operation.
SUPPLY AND GROUND CONSIDERATIONS
SPT suggests that all power supply pins (AVDD) be tied
together and decoupled using a 0.1 µF ceramic capacitor in
parallel with a 10 µF tantalum capacitor.
EXTERNAL REFERENCE VOLTAGE (VREF1)
A +3 V (±10%) voltage reference should be externally gener-
ated for the VREF1 pin using the simple voltage divider shown
in figure 4. Connect a 0.1 µF bypass capacitor between
VREF1 and AVSS as close to the pin as possible.
EXTERNAL REFERENCE VOLTAGE (VREF2)
VREF2 needs to be externally connected to AVDD through a
1.2 kΩ (5%) resistor. Connect a 0.1 µF bypass capacitor
between VREF2 and AVSS as close to the pin as possible.
CONTROL VOLTAGE DECOUPLING (VCS1)
This is a decoupling pin for the control voltage internal
circuitry. An external 0.1 µF capacitor should be connected
between VCS1 and AVSS as close to the pin as possible.
FULL-SCALE ADJUST CONTROL (VCS2)
VCS2 is an external control voltage input that controls the
peak-to-peak full scale output voltage. This is the only exter-
nal voltage that has direct control over the SPT5230 output
voltage. The voltage output swings between AVDD (+5 V) and
a value controlled by VCS2.
Assuming that an output load resistor of 75 Ω is connected
between the output and AVDD, figure 2 shows what the output
voltage will be for the digital inputs all equal to logic 0, as VCS2
is varied from 2 V to 4 V. Figure 3 shows the peak-to-peak
output voltage versus VCS2 and table I shows an example in
which VCS2 is equal to 2.1 V.
CURRENT OUTPUTS
Each red, green and blue current output should have a load
resistor connected to AVDD. The resistors are typically 75 Ω
and should be kept in the 72 Ω to 85 Ω range. The outputs
should drive a high impedance load such as a voltage
follower.
OUTPUT LEVEL SHIFTING CIRCUIT
The SPT5230 voltage output will swing from +3.0 V to +4.99
V for VCS2 = 2.1 V as shown in table I. If level shifting of the
output is desired, SPT recommends use of the circuit shown
in figure 5. The desired –FS voltage is fed into the collector of
the emitter to achieve the desired level shift. (Note the phase
inversion that will occur due to the common emitter.) Choose
any appropriate video op amp with adequate power supply
head room.
Table I – Binary Codes
1 LSB = 1.953 mV, VCS2 ≈ 2.1 V
Step
0
1
2
3
.
.
.
1022
1023
Digital Input
Analog
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Out (V)
(MSB)
(LSB)
0 0 0 0 0 0 0 0 0 0 3.000000
0 0 0 0 0 0 0 0 0 1 3.001953
0 0 0 0 0 0 0 0 1 0 3.003906
0 0 0 0 0 0 0 0 1 1 3.005859
.
.
.
.
.
.
1 1 1 1 1 1 1 1 1 0 4.996094
1 1 1 1 1 1 1 1 1 1 4.998047
SPT
3
SPT5230
5/1/00
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