OM6211 데이터 시트보기 (PDF) - Philips Electronics

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OM6211

48×84 dot matrix LCD driver

Philips Electronics 

Philips Semiconductors

48 × 84 dot matrix LCD driver

Product specification

OM6211

11.2 Serial interface

The serial interface is a 3-line bidirectional interface for

communication between the microcontroller and the LCD

driver chip. The 3 lines are: SCE (chip enable), SCLK

(serial clock) and SDA (serial data). The OM6211 is

connected to SDA by two pins: SDIN (data input) and

SDOUT (data output) connected together.

11.2.1 WRITE MODE

The write mode of the interface means that the

microcontroller writes commands and data to the OM6211.

Each data packet contains a control bit D/C and a

transmission byte. If D/C is LOW, the following byte is

interpreted as a command byte (see Table 5). If D/C is

HIGH, the following byte is stored in the display data RAM.

After every data byte the address counter is incremented

automatically. Figure 11 shows the general format of the

write mode and the definition of the transmission byte.

Every command can be sent in any order to the OM6211.

The MSB of a byte is transmitted first. The serial interface

is initialized when SCE is HIGH. In this state, SCLK clock

pulses have no effect and no power is consumed by the

serial interface. A falling edge on SCE enables the serial

interface and indicates the start of a data transmission.

Figures 12, 13 and 14 show the protocol of the write

mode:

• When SCE is HIGH, SCLK clocks are ignored: during

the HIGH time of SCE the serial interface is initialized

(see Fig.12)

• At the falling edge of SCE SCLK must be LOW (see

Fig.16); for the transmission of each data bit a rising and

then a falling edge of SCLK is necessary

• SDIN is sampled at the rising edge of SCLK

• D/C indicates whether the byte is a command (D/C = 0)

or RAM data (D/C = 1); it is sampled with the first rising

SCLK edge

• If SCE stays LOW after the last bit of a command or data

byte, the serial interface expects the D/C bit of the next

byte at the next rising edge of SCLK (see Fig.13)

• A reset pulse with RES interrupts the transmission. The

data being written into the RAM may be corrupted. The

registers are cleared. If SCE is LOW after the rising

edge of RES, the serial interface is ready to receive the

D/C bit of a command or data byte (see Fig.14).

handbook, full pagewiTdtrhansmission Byte (TB) (command byte OR data byte)

D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

MSB

LSB

D/C

TB

D/C

TB

D/C

TB

Fig.11 Serial data stream, write mode.

MGU278

2002 Jan 17

18

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