P83C434CFP 데이터 시트보기 (PDF) - Philips Electronics

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P83C434CFP

8-bit microcontrollers with LCD-driver

Philips Electronics 

Philips Semiconductors

8-bit microcontrollers with LCD-driver

Product specification

P83C434; P83C834

6 FUNCTIONAL DESCRIPTION

The block diagram is shown in Fig.1. The P83C434 and

P83C834 provide all functions that are required for a user

interface. This is illustrated in the radio application detailed

in Chapter 12. In the following sections the functions of the

device are described.

6.1 Input/Output (I/O)

A total of 12 I/O lines are available.

Port 0 P0.0 to P0.7 (8 lines).

Port configuration: Quasi-bidirectional (push-pull in

emulation mode). For the Interrupt generation see

Fig.10. If one of the port lines P0.0 to P0.3 is a

logic 0 or one of the port lines P0.4 to P0.7 is equal

to the corresponding bit in the Miscellaneous

Control Register (MCON) and the corresponding bit

in the Interrupt Gate Register (IG) is a logic 1, then

an INT0 interrupt is generated.

Port 2 P2.0 to P2.3 (4 lines).

Port configuration: Quasi-bidirectional (push-pull in

emulation mode). When writing to Port 2, bits

P2.4 to P2.7 have to be fixed at HIGH. Data to be

written should be ‘1111XXXXB’.

6.1.1 EMC (ELECTROMAGNETIC COMPATIBILITY)

In order to reduce EMI (Electromagnetic Interference) the

following design measures have been taken:

• Slope control is implemented on all the I/O lines.

Rise and fall time (10% to 90%) are:

20 ns < rise/fall time < 50 ns.

• The power supply and ground pins are placed next to

each other.

• Double bonding VSS pins, i.e. 2 bondpads for each pin.

• Limiting the drive capability of:

– clock drivers and prechargers.

– segment drivers and backplane drivers for the LCD.

• External decoupling of the of the CPU supply VDD(C);

to avoid interference on the VDD line, the VDD(C) and

VDD(P) pins should be connected as illustrated in Fig.4.

handbook, halfpage

VDD

2.2 µH

VDD(C)

VDD(P)

P83C434

P83C834

MGG019

Fig.4 Avoiding interference on VDD.

handbook, full pagewidth

Q

from port latch

input data

read port pin

strong pull-up

2 oscillator

periods

p2

p1

p3

n

I1

INPUT

BUFFER

Fig.5 Standard output with switched pull-up current source.

VDD

I/O PIN

MLC926 - 1

1997 Jul 03

8

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