Philips Semiconductors
16-bit microcontroller
5.5.2 THE SPECIAL STATUS WORD (SSW)
Product specification
P90CE201
handbook, full pagewidth
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RR * IF DF RM HB BY RW HW LC * * * FC FC FC
210
MCD513
Fig.8 Special Status Word.
Table 4 Description of SSW.
SYMBOL
RR
−
IF
DF
RM
HB
BY
RW
HW
LC
−
−
−
FC2
FC1
FC0
BIT
SSW.15
SSW.14
SSW.13
SSW.12
SSW.11
SSW.10
SSW.9
SSW.8
SSW.7
SSW.6
SSW.5
SSW.4
SSW.3
SSW.2
SSW.1
SSW.0
FUNCTION
Rerun. By default this bit is a logic 0. If set to a logic 1, the CPU will not re-run the
faulty bus cycle on return from exception (RTE).
Undefined, reserved
The faulty cycle was an instruction fetch.
The faulty cycle was a data fetch.
The error occurred during a read-modify-write cycle.
High Byte
The faulty cycle was a byte transfer.
Read/Write cycle
High Word
The faulty cycle was during a long-word access.
Undefined, reserved
Undefined, reserved
Undefined, reserved
Function Code. These three bits hold the internal function code during the faulty
bus cycle. The function codes are the same as for the 68000 and affect the status
of the CPU during the faulty bus cycle. See Table 5.
Table 5 Internal function codes.
FC2
FC1
FC0
ADDRESS SPACE
0
0
0
Reserved
0
0
1
User data
0
1
0
User program
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Supervisor data
1
1
0
Supervisor program
1
1
1
Interrupt acknowledge
August 1993
15