ST24W08M6TR 데이터 시트보기 (PDF) - STMicroelectronics

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ST24W08M6TR

8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection

STMicroelectronics 

ST24/25C08, ST24/25W08

DEVICE OPERATION (cont’d)

master must NOT acknowledge the last byte out-

put, but MUST generate a STOP condition. The

output data is from consecutive byte addresses,

with the internal byte address counter automat-

ically incremented after each byte output. After a

count of the last memory address, the address

counter will ’roll-over’ and the memory will continue

to output data.

Acknowledge in Read Mode. In all read modes

the ST24/25x08 wait for an acknowledge during the

9th bit time. If the master does not pull the SDA line

low during this time, the ST24/25x08 terminate the

data transfer and switches to a standby state.

Figure 11. Read Modes Sequence

CURRENT

ADDRESS

READ

RANDOM

ADDRESS

READ

SEQUENTIAL

CURRENT

READ

SEQUENTIAL

RANDOM

READ

ACK

NO ACK

DEV SEL

DATA OUT

R/W

ACK

ACK

ACK

NO ACK

DEV SEL *

BYTE ADDR

DEV SEL *

DATA OUT

R/W

R/W

ACK

ACK

DEV SEL

DATA OUT 1

R/W

ACK

NO ACK

DATA OUT N

ACK

ACK

ACK

ACK

DEV SEL *

BYTE ADDR

DEV SEL *

DATA OUT 1

R/W

R/W

ACK

NO ACK

DATA OUT N

AI00794C

Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.

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