PCA9502 데이터 시트보기 (PDF) - NXP Semiconductors.
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PCA9502 Datasheet PDF : 25 Pages
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NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
SDA
MSB
acknowledgement signal
from receiver
SCL
S
START
condition
0
1
6
7
8
ACK
byte complete,
interrupt within receiver
Fig 6. Data transfer on the I2C-bus
0
1
2 to 7
8
ACK
clock line held LOW
while interrupt is serviced
P
STOP
condition
002aab012
data output
by transmitter
transmitter stays off of the bus
during the acknowledge clock
data output
by receiver
acknowledgement signal
from receiver
SCL from master
S
START
condition
0
1
Fig 7. Acknowledge on the I2C-bus
6
7
8
002aab013
A slave receiver must generate an acknowledge after the reception of each byte, and a
master must generate one after the reception of each byte clocked out of the slave
transmitter.
There is an exception to the ‘acknowledge after every byte’ rule. It occurs when a master
is a receiver: it must signal an end of data to the transmitter by not signalling an
acknowledge on the last byte that has been clocked out of the slave. The acknowledge
related clock, generated by the master should still take place, but the SDA line will not be
pulled down. In order to indicate that this is an active and intentional lack of
acknowledgement, we shall term this special condition as a ‘negative acknowledge’.
9.2 Addressing and transfer formats
Each device on the bus has its own unique address. Before any data is transmitted on the
bus, the master transmits on the bus the address of the slave to be accessed for this
transaction. A well-behaved slave with a matching address, if it exists on the network,
should of course acknowledge the master's addressing. The addressing is done by the
first byte transmitted by the master after the START condition.
An address on the network is seven bits long, appearing as the most significant bits of the
address byte. The last bit is a direction (R/W) bit. A ‘0’ indicates that the master is
transmitting (write) and a ‘1’ indicates that the master requests data (read). A complete
data transfer, comprised of an address byte indicating a ‘write’ and two data bytes is
shown in Figure 8.
PCA9502_3
Product data sheet
Rev. 03 — 13 October 2006
© NXP B.V. 2006. All rights reserved.
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