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9532 Datasheet PDF : 29 Pages
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NXP Semiconductors
PCA9532
16-bit I2C-bus LED dimmer
11. Dynamic characteristics
Table 14. Dynamic characteristics
Symbol Parameter
fSCL
tBUF
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tVD;ACK
tVD;DAT
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START condition
set-up time for a repeated START
condition
set-up time for STOP condition
data hold time
data valid acknowledge time
data valid time
tSU;DAT
tLOW
tHIGH
tr
tf
tSP
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
pulse width of spikes that must be
suppressed by the input filter
Port timing
tv(Q)
tsu(D)
th(D)
Reset
data output valid time
data input set-up time
data input hold time
tw(rst)
trec(rst)
trst
reset pulse width
reset recovery time
reset time
Conditions
Standard-mode
I2C-bus
Min Max
0
100
4.7
-
Fast-mode I2C-bus
Min
Max
0
400
1.3
-
4.0
-
0.6
-
4.7
-
0.6
-
LOW-level
HIGH-level
4.0
0
[1]
-
[2]
-
[2]
-
250
4.7
4.0
-
-
-
-
0.6
-
-
0
-
600
-
600
600
-
600
1500
-
600
-
100
-
-
1.3
-
-
0.6
-
1000 20 + 0.1Cb[3] 300
300 20 + 0.1Cb[3] 300
50
-
50
-
200
-
200
100
-
100
-
1
-
1
-
10
-
10
-
0
-
0
-
[4][5] 400
-
400
-
Unit
kHz
µs
µs
µs
µs
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
µs
ns
ns
ns
[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] tVD;DAT = minimum time for SDA data output to be valid following SCL LOW.
[3] Cb = total capacitance of one bus line in pF.
[4] Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
[5] Upon reset, the full delay will be the sum of trst and the RC time constant of the SDA bus.
PCA9532_4
Product data sheet
Rev. 04 — 17 March 2009
© NXP B.V. 2009. All rights reserved.
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