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PCD3353CT

8-bit microcontrollers with DTMF generator and 128 bytes EEPROM

Philips Electronics 

Philips Semiconductors

8-bit microcontrollers with DTMF generator

and 128 bytes EEPROM

Product specification

PCA3351C; 52C; 53C;

PCD3351A; 52A; 53A

8 DERIVATIVE INTERRUPTS

One derivative interrupt event is defined. It is controlled by

bits T2F and ET2I in the EPCR (see Tables 11 and 12).

The derivative interrupt event occurs when T2F is set. This

request is honoured under the following circumstances:

• No interrupt routine proceeds

• No external interrupt request is pending

• The derivative interrupt is enabled

• ET2I is set.

The derivative interrupt routine must include instructions

that will remove the cause of the derivative interrupt by

explicitly clearing T2F. If the derivative interrupt is not

used, T2F may directly be tested by the program.

Obviously, T2F can also be asserted under program

control, e.g. to generate a software interrupt.

9 TIMING

Although the PCD335xA and PCA335xC operate over a

clock frequency range from 1 to 16 MHz, fxtal = 3.58 MHz

will usually be chosen to take full advantage of the

frequency generator section.

10 RESET

In addition to the conditions given in the “PCD33XXA

Family” data sheet, all derivative registers are cleared in

the reset state.

After exit from Stop mode by a HIGH level on CE/T0,

Timer 2 proceeds from the held state.

13 INSTRUCTION SET RESTRICTIONS

• For PCD3351A and PCA3351C only:

– ROM space being restricted to 2 kbytes, the

‘SEL MB1/2/3’ instructions would define non-existing

program memory banks and should therefore be

avoided.

– RAM space being restricted to 64 bytes, care should

be taken to avoid accesses to non-existing RAM

locations.

• For PCD3352A and PCA3352C only:

– ROM space being restricted to 4 kbytes, the

‘SEL MB2/3’ instructions would define non-existing

program memory banks and should therefore be

avoided.

• For PCD3353A and PCA3353Conly:

– ROM space being restricted to 6 kbytes, the

‘SEL MB3’ instructions would define non-existing

program memory banks and should therefore be

avoided.

• For the PCD3352A, PCD3353A, PCA3352C and

PCA3353C, RAM space is restricted to 128 bytes, thus

care should be taken to avoid accesses to non-existing

RAM locations.

11 IDLE MODE

In Idle mode, the frequency generator, the EEPROM and

the Timer 2 sections remain operative. Therefore, the

IDLE instruction may be executed while an erase and/or

write access to EEPROM is in progress.

12 STOP MODE

Since the oscillator is switched off, the frequency

generator, the EEPROM and the Timer 2 sections receive

no clock. It is suggested to clear both the HGF and the

LGF registers before entering Stop mode. This will cut off

the biasing of the internal amplifiers, considerably

reducing current requirements.

The Stop mode must not be entered while an erase

and/or write access to EEPROM is in progress. The STOP

instruction may only be executed when EWP in EPCR is

zero. The Timer 2 section is frozen during Stop mode.

1999 Oct 28

19

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