PCF2113AU 데이터 시트보기 (PDF) - Philips Electronics
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PCF2113AU Datasheet PDF : 72 Pages
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Philips Semiconductors
LCD controllers/drivers
Product specification
PCF2113x
14 AC CHARACTERISTICS
VDD1 = 1.8 to 5.5 V; VDD2 = VDD3 = 2.2 to 4.0 V; VSS = 0 V; VLCD = 2.2 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
fFR
LCD frame frequency (internal clock)
VDD = 5.0 V 45
fosc
oscillator frequency (not available at any pin)
140
fOSC(ext) external clock frequency
140
tosc(st)
oscillator start-up time after power-down
note 1
−
tW(PD)
power-down HIGH-level pulse width
1
tSW(PD) tolerable spike width on PD pin
note 1
−
Timing characteristics of parallel interface; note 2
TYP.
95
250
−
200
−
−
MAX.
147
450
450
300
−
90
UNIT
Hz
kHz
kHz
µs
µs
ns
WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2113X); see Fig.27
Tcy(en)
tW(en)
tsu(A)
th(A)
tsu(D)
th(D)
enable cycle time
enable pulse width
address set-up time
address hold time
data set-up time
data hold time
500
−
220
−
50
−
25
−
60
−
25
−
READ OPERATION (READING DATA FROM PCF2113X TO MICROCONTROLLER); see Fig.28
Tcy(en)
tW(en)
tsu(A)
th(A)
td(D)
th(D)
enable cycle time
enable pulse width
address set-up time
address hold time
data delay time
data hold time
500
−
220
−
50
−
25
−
VDD1 > 2.2 V −
−
VDD1 > 1.5 V −
−
5
−
Timing characteristics of I2C-bus interface; see Fig.29; note 2
fSCL
tLOW
tHIGH
tSU;DAT
tHD;DAT
tr
tf
Cb
tSU;STA
tHD;STA
SCL clock frequency
SCL clock LOW period
SCL clock HIGH period
data set-up time
data hold time
SCL and SDA rise time
SCL and SDA fall time
capacitive bus line load
set-up time for a repeated START condition
START condition hold time
note 1 and 3
note 1 and 3
−
−
1.3
−
0.6
−
100
−
0
−
15 + 0.1 Cb −
15 + 0.1 Cb −
−
−
0.6
−
0.6
−
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
150
ns
250
ns
100
ns
400
kHz
−
µs
−
µs
−
ns
−
ns
300
ns
300
ns
400
pF
−
µs
−
µs
2001 Dec 19
41
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