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PCF2119AU/2 데이터 시트보기 (PDF) - Philips Electronics

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PCF2119AU/2
Philips
Philips Electronics Philips
PCF2119AU/2 Datasheet PDF : 68 Pages
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Philips Semiconductors
LCD controllers/drivers
Product specification
PCF2119X
8.1 Clear display
‘Clear display’ writes character code 20H into all DDRAM
addresses (the character pattern for character code 20H
must be a blank pattern), sets the DDRAM address
counter to logic 0 and returns the display to its original
position, if it was shifted. Thus, the display disappears and
the cursor or blink position goes to the left edge of the
display. Sets entry mode I/D = 1 (increment mode). S of
entry mode does not change.
The instruction ‘clear display’ requires extra execution
time. This may be allowed by checking the Busy Flag (BF)
or by waiting until the 165 clock cycles have elapsed. The
latter must be applied where no read-back options are
foreseen, as in some Chip-On-Glass (COG) applications.
8.2 Return home
‘Return home’ sets the DDRAM address counter to logic 0
and returns the display to its original position if it was
shifted. DDRAM contents do not change. The cursor or
blink position goes to the left of the first display line.
I/D and S of entry mode do not change.
8.3 Entry mode set
8.3.1 I/D
When I/D = 1 (0) the DDRAM or CGRAM address
increments (decrements) by 1 when data is written into or
read from the DDRAM or CGRAM. The cursor or blink
position moves to the right when incremented and to the
left when decremented. The cursor underline and cursor
character blink are inhibited when the CGRAM is
accessed.
When the display is off (D = 0) the chip is in partial
power-down mode:
The LCD outputs are connected to VSS
The LCD generator and bias generator are turned off.
Three oscillator cycles are required after sending the
‘display off’ instruction to ensure all outputs are at VSS,
afterwards OSC can be stopped. If the oscillator is running
during partial power-down mode (‘display off’) the chip can
still execute instructions. Even lower current consumption
is obtained by inhibiting the oscillator (OSC = VSS).
To ensure IDD <1 µA, the parallel bus pads DB7 to DB0
should be connected to VDD; RS and R/W to VDD or left
open-circuit and PD to VDD. Recovery from power-down
mode: PD back to logic 0, if necessary OSC back to VDD
and send a ‘display control’ instruction with D = 1.
8.4.2 C
The cursor is displayed when C = 1 and inhibited when
C = 0. Even if the cursor disappears, the display functions
I/D, etc. remain in operation during display data write. The
cursor is displayed using 5 dots in the 8th line (see Fig.5).
8.4.3 B
The character indicated by the cursor blinks when B = 1.
The cursor character blink is displayed by switching
between display characters and all dots on with a period of
approximately 1 second, with fblink = 5---f-2-O---2-S---2C---4-
The cursor underline and the cursor character blink can be
set to display simultaneously.
8.3.2 S
When S = 1, the entire display shifts either to the right
(I/D = 0) or to the left (I/D = 1) during a DDRAM write. Thus
it appears as if the cursor stands still and the display
moves. The display does not shift when reading from the
DDRAM, or when writing to or reading from the CGRAM.
When S = 0, the display does not shift.
8.4 Display control (and partial power-down mode)
8.4.1 D
The display is on when D = 1 and off when D = 0. Display
data in the DDRAM is not affected and can be displayed
immediately by setting D to a logic 1.
8.5 Cursor or display shift
‘Cursor/display shift’ moves the cursor position or the
display to the right or left without writing or reading display
data. This function is used to correct a character or move
the cursor through the display. In 2-line displays, the
cursor moves to the next line when it passes the last
position (40) of the line.
When the displayed data is shifted repeatedly all lines shift
at the same time; displayed characters do not shift into the
next line.
The Address Counter (AC) content does not change if the
only action performed is shift display, but increments or
decrements with the ‘cursor shift’.
2003 Jan 30
28

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