ST6200BT1 데이터 시트보기 (PDF) - STMicroelectronics

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ST6200BT1

8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET

STMicroelectronics 

ST6200C/ST6201C/ST6203C

10.9 CONTROL PIN CHARACTERISTICS

10.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Symbol

VIL

VIH

Vhys

Parameter

Input low level voltage 2)

Input high level voltage 2)

Schmitt trigger voltage hysteresis 3)

RON Weak pull-up equivalent resistor 4)

RESD ESD resistor protection

tw(RSTL)out Generated reset pulse duration

th(RSTL)in External reset pulse hold time 5)

tg(RSTL)in Filtered glitch duration 6)

Conditions

VIN=VSS

VDD=5V

VDD=3.3V

VIN=VSS

VDD=5V

VDD=3.3V

External pin or

internal reset sources

Min

Typ 1)

0.7xVDD

200

400

150

350

300

730

2.8

Max

0.3xVDD

900

1900

Unit

V

mV

kΩ

kΩ

tCPU

µs

µs

ns

Notes:

1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.

2. Data based on characterization results, not tested in production.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The RON pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results,

not tested in production.

5. All short pulse applied on RESET pin with a duration below th(RSTL)in can be ignored.

6. The reset network protects the device against parasitic resets, especially in a noisy environment.

7. The output of the external reset circuit must have an open-drain output to drive the ST6 reset pad. Otherwise the device

can be damaged when the ST6 generates an internal reset (LVD or watchdog).

Figure 63. Typical RON vs VDD with VIN=VSS

Ron [Kohm]

1000

900

800

700

600

500

400

300

200

100

3

Ta=-40°C

Ta=25°C

Ta=95°C

Ta=125°C

4

5

6

VDD [V]

81/100

1

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