HT48RA0A 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT48RA0A

8-Bit Remote Type MCU

Holtek Semiconductor 

CLR [m].i

Description

Operation

Affected flag(s)

CLR WDT

Description

Operation

Affected flag(s)

CLR WDT1

Description

Operation

Affected flag(s)

CLR WDT2

Description

Operation

Affected flag(s)

CPL [m]

Description

Operation

Affected flag(s)

HT48RA0A

Clear bit of data memory

The bit i of the specified data memory is cleared to 0.

[m].i ¬ 0

TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾¾¾¾¾¾

Clear Watchdog Timer

The WDT is cleared (clears the WDT). The power down bit (PD) and time-out bit (TO) are

cleared.

WDT ¬ 00H

PD and TO ¬ 0

TC2 TC1 TO PD OV Z AC C

¾¾

0

0 ¾¾¾¾

Preclear Watchdog Timer

Together with CLR WDT2, clears the WDT. PD and TO are also cleared. Only execution of

this instruction without the other preclear instruction just sets the indicated flag which im-

plies this instruction has been executed and the TO and PD flags remain unchanged.

WDT ¬ 00H*

PD and TO ¬ 0*

TC2 TC1 TO PD OV Z AC C

¾ ¾ 0* 0* ¾ ¾ ¾ ¾

Preclear Watchdog Timer

Together with CLR WDT1, clears the WDT. PD and TO are also cleared. Only execution of

this instruction without the other preclear instruction, sets the indicated flag which implies

this instruction has been executed and the TO and PD flags remain unchanged.

WDT ¬ 00H*

PD and TO ¬ 0*

TC2 TC1 TO PD OV Z AC C

¾ ¾ 0* 0* ¾ ¾ ¾ ¾

Complement data memory

Each bit of the specified data memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice-versa.

[m] ¬ [m]

TC2 TC1 TO PD OV Z AC C

¾

¾

¾¾¾

Ö

¾¾

Rev. 1.70

16

July 16, 2003

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