LTC1196 데이터 시트보기 (PDF) - Linear Technology
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LTC1196 Datasheet PDF : 28 Pages
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LTC1196/LTC1198
APPLICATIONS INFORMATION
Dummy Bits
The last 2 bits of the input word following the MUX Ad-
dress are dummy bits. Either bit can be a “logical one” or
a “logical zero.” These 2 bits allow the ADC 2.5 clocks to
acquire the input signal after the channel selection.
A/D Conversion Result
Both the LTC1196 and the LTC1198 have the A/D conver-
sion result appear on the DOUT line after two null bits (see
Operating Sequence in Figures 1 and 2). Data on the DOUT
line is updated on the rising edge of the CLK line. The DOUT
data should also be captured on the rising CLK edge by the
digital systems. Data on the DOUT line remains valid for a
minimum time of thDO (30ns at 5V) to allow the capture
to occur (see Figure 3).
CLK
DOUT
VIH
tdDO
thDO
VOH
VOL
1196/98 TC03
Figure 3. Voltage Waveform for DOUT Delay Time, tdDO and thDO
Unipolar Transfer Curve
The LTC1196/LTC1198 are permanently configured for
unipolar only. The input span and code assignment for this
conversion type are shown in the following figures.
Unipolar Transfer Curve
11111111
11111110
•
•
•
00000001
VIN
00000000
1196/98 AI04
Unipolar Output Code
OUTPUT CODE
11111111
11111110
•
•
•
00000001
00000000
INPUT VOLTAGE
VREF – 1LSB
VREF – 2LSB
•
•
•
1LSB
0V
INPUT VOLTAGE
(VREF = 5.000V)
4.9805V
4.9609V
•
•
•
0.0195V
0V
1196/98 AI05
Operation with DIN and DOUT Tied Together
The LTC1198 can be operated with DIN and DOUT tied
together. This eliminates one of the lines required to com-
municate to the digital systems. Data is transmitted in both
directions on a single wire. The pin of the digital systems
connected to this data line should be configurable as either
an input or an output. The LTC1198 will take control of the
data line and drive it low on the 5th falling CLK edge after
the start bit is received (see Figure 4). Therefore the port
line of the digital systems must be switched to an input
before this happens to avoid a conflict.
REDUCING POWER CONSUMPTION
The LTC1196/LTC1198 can sample at up to a 1MHz rate,
drawing only 50mW from a 5V supply. Power consumption
can be reduced in two ways. Using a 3V supply lowers the
power consumption on both devices by a factor of five,
to 10mW. The LTC1198 can reduce power even further
because it shuts down whenever it is not converting.
Figure 5 shows the supply current versus sample rate for
the LTC1196 and LTC1198 on 3V and 5V. To achieve such
a low power consumption, especially for the LTC1198,
several things must be taken into consideration.
Shutdown (LTC1198)
Figure 2 shows the operating sequence of the LTC1198.
The converter draws power when the CS pin is low and
powers itself down when that pin is high. For lowest power
consumption in shutdown, the CS pin should be driven
with CMOS levels (0V to VCC) so that the CS input buffer
of the converter will not draw current.
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119698fa
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