PLL130-08QC-R 데이터 시트보기 (PDF) - PhaseLink Corporation

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PLL130-08QC-R

High Speed Translator Buffer to PECL

PhaseLink Corporation 

PLL130-08

High Speed Translator Buffer to PECL

FEATURES

• Differential PECL output

• Single AC coupled input (min. 100mV swing).

• Input range from DC to 1.0 GHz.

• 2.5V to 3.3V operation.

• Available in 8-Pin SOIC or 3x3mm QFN.

DESCRIPTION

PIN CONFIGURATION

(TOP VIEW)

GND 1

REF_IN 2

GND 3

PECL 4

8 VDD

7 GND

6 PECL_BAR

5 VDD

The PLL130-08 is a low cost, high performance,

high speed, buffer that reproduces any input fre-

quency from DC to 1.0GHz. It provides a pair of

differential PECL output. Any input signal with at

least 100mV swing can be used as reference

signal. This chip is ideal for conversion from sine

wave, TTL, CMOS, or LVDS to PECL.

GND

GND

GND

OE^

12 11 10

13

9

8

14 PLL130-08 7

15

6

16

5

123 4

PECL_BAR

VDD

PECL

GND

BLOCK DIAGRAM

Note: ^ denotes internal pull up

REF_IN

Input

Amplifier

PECL_BAR

PECL

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1

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