HI7188(2000) 데이터 시트보기 (PDF) - Intersil

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HI7188
(Rev.:2000)

8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System

Intersil 

HI7188

It is recommended that VCM be tied to analog ground when

operating off of AVDD = +5V and AVSS = -5V supplies. VCM

also determines the headroom at the upper and lower ends

of the power supplies which is limited by the common mode

input range where the internal operational amplifiers remain

in the linear, high gain region of operation.

Sigma Delta Modulator

The sigma delta modulator is a fourth order modulator which

converts the differential analog signal into a series of one bit

outputs. The 1’s density of this data stream provides a digital

representation of the analog input. Figure 10 shows a

simplified block diagram of the analog modulator front end of

a Sigma-Delta A/D Converter. The input signal VIN comes

into a summing junction (the PGIA in this case) where the

previous modulator output is subtracted from it. The resulting

signal is then integrated and the output of the integrator goes

into the comparator. The output of the comparator is then fed

back via a one bit DAC to the summing junction. The

feedback loop forces the average of the fed back signal to be

equal to the input signal VIN.

PGIA INTEGRATOR

VIN

+

-

∫

COMPARATOR

+-

DAC

VRHI

VRLO

FIGURE 10. SIMPLE MODULATOR BLOCK DIAGRAM

Digital Section Description

A block diagram of the digital section of the HI7188 is shown

in Figure 11. This section includes an integrating filter,

averaging filters, calibration logic registers, output data RAM,

digital serial interface and a clock generator.

Integrating Filters

The integrating filter receives a stream of 1s and 0s from the

modulator at a rate of 614kHz. The 1’s density of this data

stream provides a digital representation of the analog input

signal. The integrating filter provides the low pass function

with a cutoff of 2kHz. The Integrating Filter works in concert

with the modulator and is controlled by the same clock and

reset signals. The filter integrates 201 1-bit samples from the

modulator for a valid “conversion” to be completed. At that

time the data is transferred to the Line Noise Rejection

(LNR) Filters or straight to calibration if LNR is not selected.

Line Noise Rejection

The line noise rejection section is used to eliminate a periodic

sine wave signal of either 50Hz or 60Hz line frequencies.

To understand the functionality of the HI7188 line noise

rejection (LNR), it is useful to discuss the method utilized by

a generic integrating analog to digital converter (ADC). This

ADC uses an external summing/integrating capacitor to sum

the line noise on a capacitor over one line noise cycle. The

cycle period is 16.67ms and 20ms for 60Hz and 50Hz

respectively. The ADC output is then the desired input with

the line noise summed to zero with a conversion rate equal

to the line noise frequency.

The HI7188 has the ability to do the same function as the

Integrating ADC but samples the input four times during the

line cycle (see Figure 12). For this discussion, the desired

analog input signal will be zero. The HI7188 accomplishes this

by instituting a four quadrant, four point running average

system. The microsequencer samples all eight inputs at

exactly the same point in time and for the exact amount of

time for each of the four quadrants of a single line cycle and

stores them separately. These four samples are then

summed, on a per channels basis, which results in the same

answer of the line synchronous noise as with the Integrating

ADC.

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