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Table 2.
PSD5XX Pin
Descriptions
PSD5XX Family
The following table describes the pin names and pin functions of the PSD5XX. Pins that
have multiple names and/or functions are defined by user configuration.
Pin Name
Pin Function Type
Function Descriptions
ADIO0 – ADIO15
RD
WR
CSI
RESET
CLKIN
PA0 – PA7
PB0 – PB7
PC0 – PC7
PD0 – PD7
Address/ data bus
Multiple Names
1. Read
2. E
3. DS
4. LDS
Multiple Names
1. WR
2. R/W
3. WRL
Chip Select Input
Reset Input
Input clock
I/O Port A
I/O Port B
I/O Port C
I/O Port D
I/O 1. Address/data bus, multiplexed
bus mode
2. Address bus, non-multiplexed
bus mode
I
Multiple functions
1. Read signal
2. E signal (Clock)
3. Data strobe signal
4. Low byte data strobe
I
Multiple functions
1. Write signal
2. Read-write signal
3. Low byte write signal
I
Active low, select PSD5XX.
standby mode if high.
I
Reset I/O ports, ZPLD/macrocells,
Timers and Configuration
Registers. Active low.
I
Clock input to Timers, ZPLD
macrocells, ZPLD array, and APD
counter; connect to ground if clock
input not used.
I/O Multiple functions
1. I/O port
2. ZPLD/macrocell I/O port
3. Latched address outputs
(PA0–PA7) → (A0–A7)
4. High address inputs (A16 – A23)
5. Timer outputs (PA0 – PA3)
I/O Multiple functions
1. I/O port
2. ZPLD/macrocell I/O port
3. Latched address outputs
(PB0–PB7) → (A0–A7) or (A8–A15)
4. Timer outputs (PB0-PB3)
I/O
CMOS
or
OD
Multiple functions
1. I/O port
2. ZPLD input port
3. Latched address outputs
(PC0 – PC7) → (A0–A7)
4. Data Port (D0 – D7,
non-multiplexed bus)
I/O
CMOS
or
OD
Multiple functions
1. I/O port
2. ZPLD input port
3. Latched address outputs
(PD0–PD7) → (A0–A7) or (A8–A15)
4. Data Port (D8-D15,
non-multiplexed bus)
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