PSD9342V10JT 데이터 시트보기 (PDF) - STMicroelectronics

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PSD9342V10JT

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

Pin Name Pin

PA0

29

PA1

28

PA2

27

PA3

25

PA4

24

PA5

23

PA6

22

PA7

21

PB0

7

PB1

6

PB2

5

PB3

4

PB4

3

PB5

2

PB6

52

PB7

51

PC0

20

PC1

19

PC2

18

PC3

17

PC4

14

Type

Description

These pins make up Port A. These port pins are configurable and can have the following

functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellAB0-7) outputs.

3. Inputs to the PLDs.

4. Latched address outputs (see Table 5).

I/O 5. Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA

in burst mode.

6. As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.

7. D0/A16-D3/A19 in M37702M2 mode.

8. Peripheral I/O mode.

Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However,

PA4-PA7 can be configured as CMOS or Open Drain Outputs.

These pins make up Port B. These port pins are configurable and can have the following

functions:

1. MCU I/O – write to or read from a standard output or input port.

I/O

2. CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.

3. Inputs to the PLDs.

4. Latched address outputs (see Table 5).

Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However,

PB4-PB7 can be configured as CMOS or Open Drain Outputs.

PC0 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC0) output.

I/O 3. Input to the PLDs.

4. TMS Input2 for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC1 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC1) output.

I/O 3. Input to the PLDs.

4. TCK Input2 for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC2 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

I/O

2. CPLD macrocell (McellBC2) output.

3. Input to the PLDs.

4. VSTBY – SRAM stand-by voltage input for SRAM battery backup.

This pin can be configured as a CMOS or Open Drain output.

PC3 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC3) output.

I/O 3. Input to the PLDs.

4. TSTAT output2 for the JTAG Serial Interface.

5. Ready/Busy output for parallel In-System Programming (ISP).

This pin can be configured as a CMOS or Open Drain output.

PC4 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC4) output.

3. Input to the PLDs.

I/O 4. TERR output2 for the JTAG Serial Interface.

5. Battery-on Indicator (VBATON). Goes High when power is being drawn from the

external battery.

This pin can be configured as a CMOS or Open Drain output.

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