RT8856 데이터 시트보기 (PDF) - Richtek Technology

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RT8856

Multi-Phase PWM Controller for CPU Core Power Supply

Richtek Technology 

RT8856

Frequency Setting

High frequency operation optimizes the application for

smaller component size, but trads off efficiency due to

higher switching losses. This may be acceptable in ultra-

portable devices where the load currents are lower and

the controller is powered from a lower voltage supply. Low

frequency operation offers the best overall efficiency at

the expense of component size and board space.

Connect a resistor (RFS) between FS and ground to set

the switching frequency (fSW) per phase :

RFS (kΩ)

=

300(kHz) × 33(kΩ)

fSW (kHz)

(14)

A resistor of 5kΩ to 50kΩ corresponds to switching

frequency of 1MHz to 200kHz, respectively.

Soft-Start and Mode Change Slew Rates

The RT8856 uses 2 slew rates for various modes of

operation. These two slew rates are internally determined

by commanding one of two bi-directional current sources

on to the SOFT pin (ISS). The 7-bit VID DAC and the

precision voltage reference are referred to RGND for

accurate remote sensing. Hence, connect a capacitor

(CSOFT) from SOFT pin to RGND for controlling the slew

rate as shown in Figure 4. The capacitance of capacitor is

restricted to be larger than 10nF. The voltage on SOFT

pin (VSOFT) is higher than the reference voltage of the error

amplifier at about 0.9V.

The first current of typically 20μA is used to charge or

discharge the CSOFT during soft-start, soft-shutdown. The

second current of typically 100μA is used during other

voltage transitions, including VID change and transitions

between operation modes.

The IMVP6.5 specification specifies the critical timing

associated with regulating the output voltage. The symbol,

SLEWRATE, as given in the IMVP6.5 specification will

determine the choice of the SOFT capacitor, CSOFT, by the

following equation :

CSOFT (nF)

=

ISS (μA )

SLEWRATE(mV

/

μs)

(15)

Power Up Sequence

With the controller's VCC voltage above the POR threshold

(typ. 4.3V), the power-up sequence begins when VRON

exceeds the 3.3V logic high threshold. Approximately

20μs later, SOFT and VCORE starts ramping up to boot

voltage (1.1V) with maximum phases. The slew rate during

power-up is 20μA/CSOFT. The RT8856 pulls CLKEN low

after VVSEN rises above 1V for 73μs. Right after CLKEN

goes low, SOFT and VCORE starts ramping to first DAC

value. After CLKEN goes low for approximate 4.7ms,

PGOOD is asserted HIGH. DPRSLPVR and PSI are valid

right after PGOOD is asserted. UVP is masked as long

as VSOFT is less than 1V.

VCC 4.3V

POR

VRON

VID

XX

VCORE

PWM

Hi-Z

1.1V

1V

MAX Phases

DPRSLPVR

XX

PSI

XX

CLKEN

PGOOD

4.1V

Valid

x

x

DPRSLPVR/PSI

Defined

0.2V

MAX Phases Pull Low

Valid

XX

Valid

XX

73µs typ. 4.7ms typ.

Figure 5. Timing Diagram for Power-Up and Power-Down

Power Down

When VRON goes low, the RT8856 enters low-power

shutdown mode. PGOOD is pulled low immediately and

VSOFT ramps down with slew rate of 20μA/CSOFT. VVSEN

also ramps down following VSOFT with maximum phases.

After VVSEN falls below 200mV, the RT8856 turns off both

high side and low side MOSFETs. A discharging resistor

at VSEN will be enabled and the analog part will be turned

off.

Deeper Sleep Mode Transitions

After DPRSLPVR goes high, the RT8856 immediately

disables phase 2 (UGATE2 and LGATE2 forced low) and

enters 1-phase deeper sleep mode operation. If the VIDs

are set to a lower voltage setting, the output drops at a

rate determined by the load and the output capacitance.

The internal target VSOFT still ramps as before, and UVP,

OCP and OVP are masked for 73μs.

www.richtek.com

18

DS8856-03 June 2011

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