RT8862 데이터 시트보기 (PDF) - Richtek Technology

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RT8862

Advanced 4/3/2/1-Phase PWM Controller with Embedded Drivers for CPU Core Power Supply

Richtek Technology 

RT8862

Application Information

The RT8862 is a 4/3/2/1-phase synchronous buck DC/DC

converter with 2 embedded MOSFET drivers. The internal

VID DAC is designed to interface with the Intel VR11.x/

10.x and AMD K8/K8_M2 compatible CPUs.

Power Ready Detection

During start-up, the RT8862 will detect VCC12, VCC5 and

VTT. When VCC12 > 9.6V, VCC5 > 4.6V and VTT > 0.85V,

POR will go high. POR (Power On Reset) is the internal

signal to indicate all powers are ready to let the RT8862

and the companioned MOSFET drivers work properly.

When POR = L, the RT8862 will try to turn off both high

side and low side MOSFETs.

VCC12

VCC5

VTT

9.6V

4.6V

0.85V

CMP

+

-

CMP

+

-

CMP

+

-

POR

POR : Power On Reset

Figure 1. Circuit for Power Ready Detection

Phase Detection

The number of operational phases is determined by the

internal circuitry that monitors the ISNn voltages during

start up. Normally, the RT8862 operates as a 4-phase

PWM controller. Pull ISN4 and ISP4 to VCC5 programs

3-phase operation. Pull ISN3 and ISP3 to VCC5 programs

2-phase operation. The RT8862 detects the voltage of

ISN4 and ISN3 POR rising edge. At the rising edge, the

RT8862 detects whether the voltage of ISN4 and ISN3 are

higher than “VCC5 − 1V” respectively to decide how many

phases should be active. Phase detection is only active

during start up. When POR = H, the number of operational

phases is determined and latched. The unused PWM pins

can be connected either to 5V, GND or left floating.

Phase Switching Frequency

The phase switching frequency of the RT8862 is set by

an external resistor connected from the RT pin to GND.

The frequency follows the graph in Figure 2.

Frequency vs. RRT

1200

1000

800

600

400

200

0

0

40

80 120 160 200 240 280

RRT (kkΩoh) m)

Figure 2. RRT vs Phase Switching Frequency

Soft Start

Output current of OPSS (ISS) is limited and variant

VDAC

OPSS

+

-

SS

CSS

SSQ

+-

EAP

(ErrorAmp positive input)

ADJ

RADJ

NTC

Figure 4. Circuit for Soft Start and Dynamic VID

The VOUT start-up time is set by a capacitor from the SS

pin to GND. In power_on_reset state (POR = L), the SS

pin is held at GND. After power_on_reset stae (POR = H)

and an extra delay of 1600μs, VSS and VSSQ begin to rise

till VSSQ = VBOOT. When VSSQ = VBOOT, the RT8862 stays

in this state for 800μs, waiting for valid VID code sent by

CPU. After receiving valid VID code, VOUT continues

ramping up or down to the voltage specified by VID code.

Before PWRGD = H, output current of OPSS (ISS) is

limited to μA (ISS1). When PWRGD = H, ISS is limited to

80μA (ISS2). The soft start waveform is shown in Figure 5.

www.richtek.com

20

DS8862-01 April 2011

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