RT8280
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
Four Layer PCB
Copper Area
70mm2
50mm2
30mm2
10mm2
Min.Layout
25
50
75
100
125
Ambient Temperature (°C)
Figure 8. Derating Curves for RT8280 Package
Layout Consideration
Follow the PCB layout guidelines for optimum performance
of the RT8280.
` Keep the traces of the main current paths as short and
wide as possible.
` Place the input capacitor as close as possible to the
device pins (VIN and GND).
` SW node experiences high frequency voltage swing and
should be kept in a small area. Keep analog components
away from the SW node to prevent stray capacitive noise
pick up.
` Connect the feedback network behind the output
capacitors. Keep the loop area small. Place the feedback
components near the RT8280.
` Connect all analog grounds to a common node and then
connect the common node to ground behind the output
capacitors.
` An example of the PCB layout guide is shown in Figure
9 for reference.
GND
VIN SW GND
The feedback components
must be connected as close
to the device as possible.
Input capacitor must
be placed as close
to the IC as possible.
CIN
BOOT
D
CS RS
VIN
SW
GND
COUT
L
8
2
7
GND
3
6
9
4
5
RRT CC
RT
EN
CP RC
COMP
R1
FB
R2 VOUT
VOUT
SW should be connected to inductor by
wide and short trace. Keep sensitive
components away from this trace.
Figure 9. PCB Layout Guide
GND
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
14
is a registered trademark of Richtek Technology Corporation.
DS8280-02 March 2012