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RTL8139D-GR 데이터 시트보기 (PDF) - Realtek Semiconductor

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RTL8139D-GR Datasheet PDF : 67 Pages
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RTL8139DL
Datasheet
Bit
R/W
Symbol
Description
frame alignment error (FAE). The collided frame will not be recognized
as CRC error if the length of this frame is shorter than 16 byte.
0
R/W
ROK
Receive (Rx) OK: In normal mode, indicates the successful completion
of a packet reception. In early mode, indicates that the Rx byte count of
the arriving packet exceeds the early Rx threshold.
5.7. Transmit Configuration Register
(Offset 0040h-0043h, R/W)
This register defines the Transmit Configuration for the RTL8139D(L). It controls such functions as
Loopback, Heartbeat, Auto Transmit Padding, programmable Interframe Gap, Fill and Drain Thresholds,
and maximum DMA burst size.
Bit
31
30-26
R/W
-
R
Symbol
-
HWVERID_A
Description
Reserved
Hardware Version ID A:
Bit30 Bit29 Bit28 Bit27 Bit26
RTL8139
1
1
0
0
0
RTL8139A 1 1 1 0 0
RTL8139A-G 1 1 1 0 1
RTL8139B 1 1 1 1 0
RTL8130
1
1
1
1
0
RTL8139C 1 1 1 0 1
RTL8100
1
1
1
1
0
RTL8100B/ 1 1 1 0 1
8139D
RTL8139C+ 1 1 1 0 1
RTL8101
1
1
1
0
1
Reserved
Other combination
Bit23
0
0
0
0
0
0
1
0
1
1
Bit22
0
0
0
0
0
0
0
1
0
1
25-24
23-22
21-19
18, 17
R/W
IFG1, 0
Interframe Gap Time: This field allows the user to adjust the
interframe gap time below the standard: 9.6 us for 10Mbps, 960 ns for
100Mbps. The time can be programmed from 9.6 us to 8.4 us (10Mbps)
and 960ns to 840ns (100Mbps). Note that any value other than (1, 1)
will violate the IEEE 802.3 standard.
The formula for the inter frame gap is:
10 Mbps
8.4us + 0.4(IFG(1:0)) us
100 Mbps
840ns + 40(IFG(1:0)) ns
R
HWVERID_B Hardware Version ID B
-
-
Reserved
R/W
LBK1, LBK0 Loopback test: There will be no packet on the TX+/- lines under the
Loopback test condition. The loopback function must be independent of
the link state.
00 : normal operation
01 : Reserved
10 : Reserved
11 : Loopback mode
Single Chip Multifunction 10/100 Ethernet Controller w/Power Management 14 Track ID: JATR-1076-21 Rev. 1.2

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