S-1172B29-E6T1G 데이터 시트보기 (PDF) - Seiko Instruments Inc

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S-1172B29-E6T1G

HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR

Seiko Instruments Inc 

HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR

S-1172 Series

Rev.1.1_00

„ Operation

1. Basic operation

Figure 13 shows the block diagram of the S-1172 Series.

The error amplifier compares the reference voltage (Vref) with Vfb, which is the output voltage resistance-divided by

feedback resistors Rs and Rf. It supplies the gate voltage necessary to maintain the constant output voltage which

is not influenced by the input voltage and temperature change, to the output transistor.

VIN

Current

supply

Vref

Error amplifier

−

+

*1

Rf

VOUT

Vfb

Reference voltage

circuit

Rs

VSS

*1. Parasitic diode

Figure 13

2. Output transistor

In the S-1172 Series, a low on-resistance P-channel MOS FET is used as the output transistor.

Be sure that VOUT does not exceed VIN + 0.3 V to prevent the voltage regulator from being damaged due to inverse

current which flows, because of a parasitic diode between the VIN and VOUT pin, when the potential of VOUT

became higher than VIN.

14

Seiko Instruments Inc.

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